Computational memory with zero disable and error detection

A processing device comprising:

• an array of processing elements, each processing element including logic to perform an operation in response to input to the logic being changed, each processing element connected to memory to store data for the operation;
• interconnections among the array of processing elements to provide direct communication among neighboring processing elements of the array of processing elements, wherein a processing element of the array of processing elements is connected to a neighbor processing element via an input selector to selectively take output of the neighbor processing element as input to the processing element for the operation;
• wherein the processing element further includes:
• an input zero detector to detect whether the input from the neighbor processing element contains zero;
• and
• a zero disable circuit connected to the input zero detector, wherein when the input from the neighbor processing element contains zero, the zero disable circuit is to control the input from the neighbor processing element and respective data of the memory to both appear as unchanged to the logic to prevent the logic unit from performing the operation.