US 11,881,397 B2 · Semiconductor device with a porous portion, wafer composite and method of manufacturing a semiconductor device

Abstract

A semiconductor substrate includes a base portion, an auxiliary layer and a surface layer. The auxiliary layer is formed on the base portion. The surface layer is formed on the auxiliary layer. The surface layer is in contact with a first main surface of the semiconductor substrate. The auxiliary layer has a different electrochemical dissolution efficiency than the base portion and the surface layer. At least a portion of the auxiliary layer and at least a portion of the surface layer are converted into a porous structure. Subsequently, an epitaxial layer is formed on the first main surface.

Claims20

Dependent claims

A wafer composite, comprising:

a base portion;
a porous structure comprising:
a coarse-porous layered portion formed on the base portion;
a first fine-porous columnar portion formed on a first portion of the coarse-porous layered portion;
a non-porous portion formed on a second portion of the coarse-porous layered portion;
and
a second fine-porous columnar portion formed on a third portion of the coarse-porous layered portion, wherein the non-porous portion is between the first fine-porous columnar portion and the second fine-porous columnar portion;
and
an epitaxial layer formed directly on the first fine-porous columnar portion, the non-porous portion and the second fine-porous columnar portion.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application

17/869,524Filed 20 Jul 2022 · division

Priority

DE 102019105677.26 Mar 2019

Published

US 2022/0359194 A110 Nov 2022

Granted

23 Jan 2024

Term ends

Not estimatedThe source records don’t support an estimate.

Classification18 codes

H10D 62/40
Semiconductor bodies, or regions thereof, of devices having potential barriers: crystalline structures
H10P 14/665
Characterised by the type of materials: porous materials
H10D 8/411
Diodes: pN diodes having planar bodies
H10D 12/441
Insulated-gate bipolar transistors [IGBT]: vertical IGBTs

Family

Application16/811,192Parent of this division · filed 6 Mar 2020

US 2022/0359194 A1Pre-grant publication · published 10 Nov 2022

US 11,476,111 B2Parent of this division

US 2020/0286730 A1Published application

US 11,881,397 B2This patent

From the US filing history. Foreign family members aren’t listed.

Semiconductor device with a porous portion, wafer composite and method of manufacturing a semiconductor device

Life of this patent

Semiconductor device with a porous portion, wafer composite and method of manufacturing a semiconductor device

Life of this patent

Abstract

Claims20