US 11,880,683 B2 · Packed 16 bits instruction pipeline

Abstract

Systems, apparatuses, and methods for efficiently processing arithmetic operations are disclosed. A computing system includes a processor capable of executing single precision mathematical instructions on data sizes of M bits and half precision mathematical instructions on data sizes of N bits, which is less than M bits. At least two source operands with M bits indicated by a received instruction are read from a register file. If the instruction is a packed math instruction, at least a first source operand with a size of N bits less than M bits is selected from either a high portion or a low portion of one of the at least two source operands read from the register file. The instruction includes fields storing bits, each bit indicating the high portion or the low portion of a given source operand associated with a register identifier specified elsewhere in the instruction.

Claims20

Dependent claims

A processor comprising:

a register file configured to store data;
a plurality of arithmetic logic units (ALUs);
and
circuitry configured to:
receive a first instruction;
read, from the register file, an M-bit source operand indicated by the first instruction, the M-bit source operand comprising a plurality of N-bit source operands;
in response to the first instruction comprising a packed math operation, execute the packed math operation to perform a plurality of operations on data with a size of N bits, wherein to execute the packed math operation the circuitry is configured to:
responsive to fewer than all of the plurality of N-bit source operands having been sent to an ALU, repeatedly send an N-bit source operand of the plurality of N-bit source operands to an ALU of the plurality of ALUs until all of the plurality of N-bit source operands have been sent;
and
responsive to all of the plurality of N-bit source operands having been sent to an ALU of the plurality of ALUs,
send an indication to each of the plurality of ALUs specifying a same operation to perform on data with a size of N bits.

8 more elements

A system for performing arithmetic operations, the system comprising:

a processor comprising circuitry;
and
a non-transitory computer readable storage medium comprising program instructions operable to process half-precision operations, wherein the program instructions when executed by the processor cause the system to:
store data in a register file;
read, from the register file, one or more M-bit source operands indicated by a first instruction;
in response to the first instruction comprising a packed math operation, executing the packed math operation to perform two separate operations on data with a size of N bits, where N and M are integers and N is less than M, said executing comprising:
select an M-bit source operand of the one or more M-bit source operands, the M-bit source operand comprising a plurality of N-bit source operands;
responsive to fewer than all of the plurality of N-bit source operands having been sent to an ALU of a plurality of ALUs, repeatedly send an N-bit source operand of the plurality of N-bit source operands to an ALU of the plurality of ALUs until all of the plurality of N-bit source operands have been sent;
and
responsive to all of the plurality of N-bit source operands having been sent to an ALU of the plurality of ALUs,
send an indication to each of the plurality of ALUs specifying a same operation to perform on data with a size of N bits.

8 more elements

Dependencies are inferred from the claim text.

Packed 16 bits instruction pipeline

Life of this patent

Packed 16 bits instruction pipeline

Life of this patent

Abstract

Claims20