Hybrid analog/digital equalizer architecture for high-speed receiver

Equalization circuitry for a data channel in an integrated circuit device, the equalization circuitry comprising:

• an analog equalization circuitry portion coupled to the data channel, including interleaver circuitry configured to disperse incoming signals to a plurality of interleaved equalization blocks, each interleaved equalization block in the plurality of equalization blocks comprising a feed-forward equalization circuitry portion, a decision-feedback equalization circuitry portion and a decision circuitry portion;
• and
• a digital signal processing circuitry portion downstream of the analog equalization circuitry portion, the digital signal processing circuitry portion being configured to generate control signals to control the analog equalization circuitry portion, the digital signal processing circuitry portion also including a digital equalization circuitry portion configured to operate on an output of the analog equalization circuitry portion;
• wherein:
• each respective interleaved equalization block in the plurality of equalization blocks comprises a probe slicer configured to output estimated signal properties for use by the digital signal processing circuitry portion, the estimated signal properties excluding effects of analog circuitry in the respective interleaved equalization block.