Buffer memory adapted to implment calculations having operands as data
AssigneesCommissariat A L'energie Atomique Et Aux Energies Alternatives, Universite D'Aix-Marseille, Centre National De La Recherche Scientifique
InventorsValentin Egloff, Jean-Philippe Noel, Jean-Michel Portal
Life of this patent
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Abstract
The present description concerns a memory device (200) including a non-volatile memory circuit (101); a buffer memory circuit (203) comprising a volatile memory circuit (221); an input-output circuit (105); a first data link (104) coupling the non-volatile memory circuit (101) to the buffer memory circuit (203); a second data link (106) coupling the buffer memory circuit (203) to the input-output circuit (105); and a control circuit (225), wherein the buffer memory circuit (203) is adapted to implementing calculations having as operands data stored in the volatile memory circuit (221).
Claims13
Memory device comprising:
- a non-volatile memory circuit;
- a buffer memory circuit comprising a volatile memory circuit;
- an input-output circuit;
- a first data link coupling the non-volatile memory circuit to the buffer memory circuit;
- a second data link coupling the buffer memory circuit to the input-output circuit;
- and
- a control circuit,
- wherein the buffer memory circuit is adapted to implementing calculations having as operands data stored in the volatile memory circuit, the control circuit being adapted to receiving instructions via the input-output circuit, and of accordingly controlling data transfers between the non-volatile memory circuit and the buffer memory circuit via the first data link, data transfers between the buffer memory circuit and the input-output circuit via the second data link, and the implementation of calculation operations within the buffer memory circuit,
- wherein the control circuit controls the buffer memory circuit to manage the volatile memory circuit like a cache memory,
- and wherein the buffer memory circuit integrates a lookup table for monitoring the validity of the data stored in the volatile memory circuit and matching addresses of the data stored in the volatile memory circuit and addresses of the data in the non-volatile memory circuit.
Memory device comprising:
- a non-volatile memory circuit;
- a buffer memory circuit comprising a volatile memory circuit;
- an input-output circuit;
- a first data link coupling the non-volatile memory circuit to the buffer memory circuit;
- a second data link coupling the buffer memory circuit to the input-output circuit;
- and
- a control circuit,
- wherein the buffer memory circuit is adapted to implementing calculations having as operands data stored in the volatile memory circuit, the control circuit being adapted to receiving instructions via the input-output circuit, and of accordingly controlling data transfers between the non-volatile memory circuit and the buffer memory circuit via the first data link, data transfers between the buffer memory circuit and the input-output circuit via the second data link, and the implementation of calculation operations within the buffer memory circuit,
- wherein the control circuit controls the buffer memory circuit to manage the volatile memory circuit like a cache memory,
- and wherein the control circuit is adapted to receiving calculation instructions via the input-output circuit, each calculation instruction comprises a first field defining a type of operation to be implemented, a second field defining operand addresses, and a third field defining an address for rewriting a result of the operation.
Dependencies are inferred from the claim text.