Method and system for high speed decision-feedback equalization (DFE)

Abstract

An electronic-system for implementing decision-feedback equalization (DFE) includes a first stage including a first-amplifier. The first amplifier including an in-built adder circuit. The first amplifier being configured to charge one or more output nodes of the first amplifier to a first voltage using a summed signal based on input data and a feedback signal in response to a first-clock variation, wherein the feedback signal is a partially-regenerated analog output from a regenerating amplifier. A second stage is includes a second amplifier configured as the regenerating amplifier and connected to the one or more output nodes of the first amplifier, the second amplifier configured to amplify charged output nodes of the second stage to a second voltage in response to a second-clock variation and apply a regenerative gain to the amplified second-voltage during the second-clock variation to generate the partially-regenerated analog output. A third stage includes a slave latch that is configured to resolve the partially-regenerated analog output at the output nodes of the second stage into non-return to zero (NRZ) digital values at an output of the third stage.

Dependencies are inferred from the claim text.