Digital radio frequency transmitter and wireless communication device including the same

A wireless communication device comprising:

• a first switched-capacitor digital-to-analog converter (SC-DAC) circuit including a plurality of first paths, each including a first amplifier and a first capacitor, the first SC-DAC circuit configured to receive a plurality of first pattern signals in parallel and output a first radio frequency (RF) signal by summing the plurality of first pattern signals;
• a second SC-DAC circuit including a plurality of second paths, each including a second amplifier and a second capacitor, the second SC-DAC circuit configured to receive a plurality of second pattern signals in parallel and output a second RF signal by summing the plurality of second pattern signals;
• a third SC-DAC circuit including a plurality of third paths, each including a third amplifier and a third capacitor, the third SC-DAC circuit configured to receive a plurality of third pattern signals in parallel and output a third RF signal by summing the plurality
• processing circuitry configured to generate the plurality of first pattern signals, the plurality of second pattern signals, and the plurality of third pattern signals, based on patterns of inphase (I)-quadrature (Q) binary data pairs and patterns of inverted I-Q binary data pairs, the plurality of second pattern signals lagging the plurality of first pattern signals by a first phase, and the plurality of third pattern signals lagging the plurality of first pattern signals by a second phase;
• and
• a first output terminal connected to an output terminal of each of the first through third SC-DAC circuits and configured to output an RF analog signal by summing the first through third RF signals,
• wherein a magnitude of the second RF signal is greater than a magnitude of each
• of the first and third RF signals to remove an n-th harmonic component of the RF analog signal, where “n” is an integer of at least 3.

A wireless communication device comprising:

• a first switched-capacitor digital-to-analog converter (SC-DAC) circuit including a plurality of first paths, each including a first amplifier and a first capacitor, the first SC-DAC circuit configured to receive a plurality of first pattern signals in parallel and output a first radio frequency (RF) signal by summing the plurality of first pattern signals;
• a second SC-DAC circuit including a plurality of second paths, each including a second amplifier and a second capacitor, the second SC-DAC circuit configured to receive a plurality of second pattern signals in parallel and output a second RF signal by summing the plurality of second pattern signals;
• a third SC-DAC circuit including a plurality of third paths, each including a third amplifier and a third capacitor, the third SC-DAC circuit configured to receive a plurality of third pattern signals in parallel and output a third RF signal by summing the plurality of third pattern signals;
• processing circuitry configured to generate the plurality of first pattern signals, the plurality of second pattern signals, and the plurality of third pattern signals, based on patterns of inphase (I)-quadrature (Q) binary data pairs and patterns of inverted I-Q binary data pairs, the plurality of second pattern signals lagging the plurality of first pattern signals by a first phase, and the plurality of third pattern signals lagging the plurality of first pattern signals by a second phase;
• a first output terminal connected to an output terminal of each of the first through third SC-DAC circuits and configured to output an RF analog signal by summing the first through third RF signals;
• a fourth SC-DAC circuit including a plurality of fourth paths, each including a fourth amplifier and a fourth capacitor, the fourth SC-DAC circuit configured to receive first inverted pattern signals in parallel and output a fourth RF signal by summing the first inverted pattern signals;
• a fifth SC-DAC circuit including a plurality of fifth paths, each including a fifth amplifier and a fifth capacitor, the fifth SC-DAC circuit configured to receive second inverted pattern signals in parallel and output a fifth RF signal by summing the second inverted pattern signals;
• a sixth SC-DAC circuit including a plurality of sixth paths, each including a sixth amplifier and a sixth capacitor, the sixth SC-DAC circuit configured to receive third inverted pattern signals in parallel and output a sixth RF signal by summing the third inverted pattern signals;
• and
• a second output terminal connected to an output terminal of each of the fourth through sixth SC-DAC circuits and configured to output an inverted RF analog signal by summing the fourth through sixth RF signals,
• wherein the processing circuitry is further configured to generate the first inverted pattern signals by inverting the plurality of first pattern signals, the second inverted pattern signals by inverting the plurality of second pattern signals, and the third inverted pattern signals by inverting the plurality of third pattern signals.