Powergate biasing techniques for memory applications

A device comprising:

• a memory array that operates with an applied core voltage;
• a power gating circuit having only one power gating switch with a single transistor coupled in series between a core supply voltage and the memory array, wherein the single transistor receives the core supply voltage and provides the applied core voltage to the memory array, and wherein the single transistor has a single gate, and wherein the core supply voltage refers to a negative supply voltage;
• and
• a biasing stage having a plurality of transistors arranged and coupled together to receive the applied core voltage from the single transistor and then selectively activate the single transistor by applying a feedback signal to the single gate of the single transistor based on sensing a changing voltage level of the applied core voltage,
• wherein the only one power gating switch comprises a footer device that is coupled between the negative supply voltage and the memory array, and
• wherein the biasing stage uses a leakage current drawn from a settled voltage level of the core supply voltage as a reference current to bias the biasing stage itself for regulating the applied core voltage without comparing the applied core voltage with an additional reference voltage.

A system, comprising:

• a memory array coupled between a first voltage and a second voltage;
• a header device having a single power gating switch with only one transistor coupled in series between the first voltage and the memory array, wherein the only one transistor receives the first voltage as a positive supply voltage and provides an applied first voltage to the memory array based on the positive supply voltage, and wherein the only one transistor has a single gate;
• a footer device that power gates the second voltage to the memory array as an applied second voltage;
• a central biasing header stage with a plurality of transistors that are arranged and coupled together to receive the applied first voltage from the only one transistor and then selectively activate the header device with a negative voltage biasing signal by applying a feedback signal to the single gate of the single transistor based on sensing a changing voltage level of the applied first voltage;
• and
• a central biasing footer stage that selectively activates the footer device based on sensing a changing voltage level of the applied second voltage,
• wherein the central biasing header stage uses a leakage current drawn from a settled voltage level of the core supply voltage as a reference current to bias the central biasing header stage itself for regulating the applied core voltage without comparing the applied core voltage with an additional reference voltage.

A method, comprising:

• providing a core supply voltage to only one power gating transistor for operating a memory array, wherein the only one power gating transistor is coupled in series between the core supply voltage and the memory array, wherein the core supply voltage refers to a positive supply voltage;
• providing an applied core voltage to the memory array and a biasing stage by activating the only one power gating transistor with the biasing stage by way of a plurality of transistors arranged and coupled together to receive the applied core voltage from the only one power gating transistor, wherein the applied core voltage refers to a positive applied core voltage;
• power gating the core supply voltage with the biasing stage so as to provide the applied core voltage to the memory array with the only one power gating transistor, wherein the only one power gating transistor has only one gate;
• and
• selectively activating the only one power gating transistor with a feedback signal applied by the biasing stage by way of the plurality of transistors to the only one gate of the only one power gating transistor based on sensing a changing voltage level of the applied core voltage,
• wherein the biasing stage uses a leakage current drawn from a settled voltage level of the core supply voltage as a reference current to bias the biasing stage itself for regulating the applied core voltage without comparing the applied core voltage with an additional reference voltage.