Ternary logic circuit device

A circuit comprising:

• a first full adder;
• a second full adder;
• a first half adder;
• a third full adder configured to receive a sum output signal of the first full adder, a sum output signal of the second full adder, and a sum output signal of the first half adder;
• a fourth full adder configured to receive a carry output signal of the first full adder, a carry output signal of the second full adder, and a carry output signal of the first half adder;
• a second half adder configured to receive a carry output signal of the third full adder and a sum output signal of the fourth full adder;
• and
• a third half adder configured to receive a carry output signal of the second half adder and a carry output signal of the fourth full adder,
• wherein the third full adder, the second half adder, and the third half adder are configured to output voltage signals corresponding to a sum of logical values indicated by input signals applied to the first full adder, the second full adder, and the first half adder,
• wherein the first full adder, the second full adder, the third full adder, and the fourth full adder are binary full adders (BFAs),
• wherein the first half adder, the second half adder, and the third half adder are binary half adders (BHAs), and
• wherein the circuit further comprises:
• a positive ternary inverter (PTI);
• and
• a binary inverter connected between the PTI and one of the first full adder, the second full adder, and the first half adder.

A circuit comprising:

• a first full adder;
• a second full adder;
• a first half adder;
• a third full adder configured to receive a sum output signal of the first full adder, a sum output signal of the second full adder, and a sum output signal of the first half adder;
• a fourth full adder configured to receive a carry output signal of the first full adder, a carry output signal of the second full adder, and a carry output signal of the first half adder;
• a second half adder configured to receive a carry output signal of the third full adder and a sum output signal of the fourth full adder;
• and
• a ternary sum gate configured to receive a carry output signal of the second half adder and a carry output signal of the fourth full adder,
• wherein the third full adder, the second half adder, and the ternary sum gate are configured to output voltage signals corresponding to a sum of logical values indicated by input signals applied to the first full adder, the second full adder, and the first half adder.