Test method for control chip and related device

A test apparatus for a control chip, the control chip comprising a built-in self-test (BIST) circuit, and the BIST circuit comprising the test apparatus, wherein the test apparatus comprises:

• a memory status acquiring circuit, configured to acquire a current status of a memory chip in a storage device;
• a first memory determining circuit, configured to use the memory chip in an idle state as a first target memory chip when the current status of the memory chip is the idle state, to store at least some of test vectors used for testing the control chip as first test vectors in the first target memory chip, wherein the idle state is a status of the memory chip when the memory chip currently has not stored any data;
• a first test vector reading circuit, configured to read the first test vectors stored in the first target memory chip;
• a first test vector sending circuit, configured to send the first test vectors to the control chip;
• a first output information receiving circuit, configured to receive first output information returned by the control chip in response to the first test vectors;
• and
• a first test result acquiring circuit, configured to acquire a first test result of the control chip based on the first output information and the first test vectors corresponding to the first output information.