Isolation of protection functions in electrical power systems during startup

An intelligent electronic device (IED) for use in an electrical power system, the IED comprising:

• a processing subsystem comprising a first processor;
• a memory subsystem comprising a first memory section and a second memory section, the first memory section including a first firmware image to provide one or more protection functions to at least one of monitor for at least one fault and mitigate for at least on fault in the electrical power system, the second memory section including a second firmware image to provide one or more non-protection functions relating to the electrical power system;
• a memory management subsystem in communication with the processing subsystem to:
• during a startup procedure for the one or more protection functions, enable memory access only between the first processor and only the first memory section to initialize the one or more protection functions while disabling memory access between the first processor and the second memory section before and during the initialization of the one or more protection functions;
• and
• only after the startup procedure for the one or more protection functions has completed, enable memory access between the first processor and the second memory section for a startup procedure for the one or more non-protection functions;
• and
• a protection subsystem to provide the one or more protection functions to at least a portion of the electrical power system.

A method of operating intelligent electronic device (IED) in an electrical power system, the method comprising:

• during a startup of the IED, initially implementing, on a first processing unit of the IED, protection computing instructions from a first memory section to at least one of monitor for or mitigate at least one fault in the electrical power system;
• only after implementing the protection computing instructions from the first memory section, implementing, on the first processing unit, additional computing instructions from the second memory section separately from the protection computing instructions from the first memory section;
• and
• disabling the additional computing instructions from the second memory section from being accessed by the first processing unit and implemented on the first processing unit before and while the protection computing instructions from the first memory section are being implemented.