Semiconductor memory having both volatile and non-volatile functionality and method of operating
AssigneeZeno Semiconductor, Inc.
InventorYuniarto Widjaja
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Abstract
Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.
Claims20
A semiconductor memory device comprising a plurality of memory strings to form a grid of semiconductor memory cells, each said memory string comprises a plurality of memory cells connected in series, wherein each said memory cell comprises:
- a floating body region configured to be charged to a level of charge indicative of a state of said memory cell to store data as volatile memory indicative of said state of said memory cell;
- a first region in electrical contact with said floating body region;
- a second region in electrical contact with said floating body region and spaced apart from said first region;
- a floating gate or trapping layer positioned between said first and second regions and configured to receive transfer of said data stored as volatile memory and store said data as non-volatile memory indicative of said state of said memory cell;
- and
- a control gate positioned above said floating gate or trapping layer;
- wherein said level of charge stored in said floating body region determines a level of charge indicative of said data stored in said floating gate or trapping layer received by said transfer of data;
- and
- wherein said transfer of data to said floating gate or trapping layer occurs to one or more of said memory cells.
A semiconductor memory device comprising a plurality of memory strings to form a grid of semiconductor memory cells, each said memory string comprises a plurality of memory cells connected in series, wherein each said memory cell comprises:
- a floating body region configured to be charged to a level of charge indicative of a state of said memory cell to store data as volatile memory indicative of said state of said memory cell;
- a first region in electrical contact with said floating body region;
- a second region in electrical contact with said floating body region and spaced apart from said first region;
- a floating gate or trapping layer positioned between said first and second regions and configured to receive transfer of said data stored as volatile memory and store said data as nonvolatile memory indicative of said state of the memory cell;
- and
- a control gate positioned above said floating gate or trapping layer,
- wherein said level of charge indicative of said state of said memory cell stored in said floating body region determines a current flowing through said semiconductor memory cell, and
- wherein said transfer of data to said floating gate or trapping layer occurs to one or more of said memory cells.
A semiconductor memory device comprising a plurality of memory strings to form a grid of semiconductor memory cells, each said memory string comprises a plurality of memory cells connected in series, wherein each said memory cell comprises:
- a floating body region;
- and
- a floating gate or trapping layer positioned above and insulated from said floating body region;
- wherein said floating body region is configured to be charged to a level indicative of a state of said memory cell based on a charge stored in said floating gate or trapping layer, upon restoration of power to said semiconductor memory device, and
- wherein transfer of data from said floating gate or trapping layer to said floating body region upon said restoration of power occurs to one or more of said memory cells.
Dependencies are inferred from the claim text.