Memory component for deployment in a dynamic stripe width memory system
AssigneeRambus Inc.
InventorsFrederick A. Ware, John Eric Linstadt, Kenneth L. Wright
Life of this patent
Estimating the term…
Abstract
In a memory component programmed to operate in a first operating mode and having a page buffer and a fixed-width data interface, N bits of a command/address value are decoded to access one of 2N columns of data within the page-buffer, with that column of data output via the fixed-width data interface over a first burst interval. If programmed to operate in a second operating mode, M bits of the command/address value are decoded to access a larger column of data—one of 2M columns of data within the page buffer, where M<N—with that larger column of data output via the fixed-width data interface over a second burst interval longer than the first burst interval.
Claims20
A method of operation within an integrated-circuit memory component, the method comprising:
- receiving a configuration value;
- receiving a first command/address value that specifies a memory read access;
- if the configuration value specifies a first operating mode:
- decoding a first column address constituted by N bits of the first command/address value to retrieve a first quantity of data from a first one of 2N independently accessible columns of a page buffer;
- and
- outputting the first quantity of data via a fixed-width data interface of the integrated-circuit memory component over Q successive data output intervals;
- and
- if the configuration value specifies a second operating mode:
- decoding a second column address constituted by M bits of the first command/address value to access a second quantity of data from a first one of 2M independently accessible columns of the page buffer, M being smaller than N and the second quantity of data exceeding the first quantity of data;
- and
- outputting the second quantity of data via the fixed-width data interface over R successive data output intervals, R being greater than Q.
An integrated-circuit memory component:
- a programmable register to store a configuration value specifies at least one of a first operating mode or a second operating mode;
- a page buffer;
- a command/address interface to receive a first command/address value that specifies a memory read access;
- a fixed-width data interface;
- and
- control circuitry that:
- in response to the first command/address value and specification of the first operating mode, decodes a first column address constituted by N bits of the first command/address value to retrieve a first quantity of data from a first one of 2N independently accessible columns of the page buffer and outputs the first quantity of data via the fixed-width data interface over Q successive data output intervals;
- in response to the first command/address value and specification of the second operating mode, decodes a second column address constituted by M bits of the first command/address value to retrieve a second quantity of data from a first one of 2M independently accessible columns of the page buffer and outputs the second quantity of data via the fixed-width data interface over R successive data output intervals, where M is smaller than N, the second quantity of data exceeds the first quantity of data, and R is greater than Q.
An integrated-circuit memory component comprising:
- a programmable register to store a configuration value specifies at least one of a first operating mode or a second operating mode;
- a page buffer;
- a command/address interface to receive a first command/address value that specifies a memory read access;
- a fixed-width data interface;
- means, responsive to the first command/address value and specification of the first operating mode, for decoding a first column address constituted by N bits of the first command/address value to retrieve a first quantity of data from a first one of 2N independently accessible columns of the page buffer and outputting the first quantity of data via the fixed-width data interface over Q successive data output intervals;
- and
- means, responsive to the first command/address value and specification of the second operating mode, for decoding a second column address constituted by M bits of the first command/address value to retrieve a second quantity of data from a first one of 2M independently accessible columns of the page buffer and outputting the second quantity of data via the fixed-width data interface over R successive data output intervals, where M is smaller than N, the second quantity of data exceeds the first quantity of data, and R is greater than Q.
Dependencies are inferred from the claim text.