Partially and fully parallel normaliser
AssigneeImagination Technologies Limited
InventorTheo Alan Drane
Life of this patent
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Abstract
Hardware logic arranged to normalise (or renormalise) an n-bit input number is described in which at least a proportion of a left shifting operation is performed in parallel with a leading zero count operation. In various embodiments the left shifting and the leading zero count are performed independently. In various other embodiments, a subset of the bits output by a leading zero counter are input to a left shifter and the output from the left shifter is input to a renormalisation block which completes the remainder of the left shifting operation independently of any further input from the leading zero counter.
Claims13
Hardware logic arranged to normalize or renormalize a binary number, the hardware logic comprising:
- a zero counter arranged to count leading or trailing zeros in the binary number;
- and
- a shifter arranged to shift the binary number;
- wherein at least a portion of the shift is performed in parallel with the count.
A method of normalizing or renormalizing a binary number by using hardware logic having a counter and a shifter, the method comprising:
- counting, with the counter of the hardware logic, leading or trailing zeros in the binary number;
- and
- shifting, with the shifter of the hardware logic, the binary number, and wherein at least a portion of the shifting is performed in parallel with the counting.
A non-transitory computer readable storage medium having stored thereon computer executable program code that when executed causes at least one processor comprising hardware logic having a counter and a shifter to
- count, with the counter of the hardware logic, leading or trailing zeros in a binary number;
- and
- shift, with the shifter of the hardware logic, the binary number, wherein at least a portion of the shift is performed in parallel with the count.
Dependencies are inferred from the claim text.