Serdes link training

A system comprising:

• an upstream port;
• a downstream port coupled to the upstream port by one or more links compliant with a Peripheral Component Interconnect Express (PCIe) protocol, the downstream port comprising a transmission/reception settings register;
• a nonvolatile memory;
• the downstream port comprising downstream port logic to:
• determine equalization parameter values for the one or more links interconnecting the upstream port with the downstream port for a plurality of data rates including a first data rate and a second data rate;
• store the equalization parameter values in the nonvolatile memory;
• operate the one or more links at the first data rate;
• determine that the one or more links are to change from the first data rate to the second data rate;
• determine that the upstream port and the downstream port support equalization bypass from information in a training set;
• write equalization parameter values for the second data rate from the nonvolatile memory to the transmission/reception settings register of the downstream port;
• and
• use the equalization parameter values to operate the one or more links.

A computer program product tangibly embodied on non-transitory computer-readable media, the computer program product comprising code that when executed cause an upstream port to:

• perform a initialization sequence of one or more input/output links between the upstream port and a downstream port, the initialization sequence comprising link training the one or more input/output links;
• determine equalization parameters for the one or more input/output links for a plurality of data rates including for a first data rate and for a second data rate;
• store the equalization parameters in a nonvolatile memory;
• operate the one or more links at a first data rate;
• determine that the one or more links are to operate at a second data rate different from the first data rate;
• determine that the upstream port and the downstream port support equalization bypass based on information in a training set;
• retrieve the stored equalization parameter values for the downstream port from the nonvolatile memory for the second data rate;
• write the stored equalization parameter values for the downstream port to a register associated with the downstream port;
• and
• use the equalization parameter values as equalization parameters for the downstream port for operating the one or more links interconnecting the upstream port with the downstream port.