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US 11,855,661 B2Granted
Multiplier and operator circuit
AssigneeHuawei Technologies Co., Ltd.
InventorsTuanbao Fan, Yuexing Jiang, Xiaoshan Shi, Rongjun Wang
Life of this patent
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Abstract
A multiplier is configured to implement multiplication of a first value of M bits and a second value of N bits, and includes P groups of encoders and W layers of inversion compressors. Each group include N encoders and are configured to encode a part of bits in the second value, and a group selection signal and a symbol control input signal corresponding to the each group. The group selection signal and the symbol control input signal are generated based on a part of bits in the first value, and the P groups of encoders perform encoding to obtain P partial products. The W layers of inversion compressors are configured to compress the P partial products.
Claims20
A multiplier configured to implement multiplication of a first value of M bits and a second value of N bits, wherein M and N are integers greater than 1, the multiplier comprising:
- P groups of encoders, each encoder group of the P groups of encoders comprising N encoders, the each encoder group configured to encode a part of bits in the second value, a group selection signal, and a symbol control input signal, the symbol control input signal corresponding to the each encoder group using non-inversion encoding operators or inversion encoding operators to obtain one partial product, the group selection signal and the symbol control input signal being generated based on a part of bits in the first value, and the P groups of encoders performing encoding to obtain P partial products;
- and
- W layers of inversion compressors coupled to the P groups of encoders, each encoder group of the P groups of encoders comprising N encoders, W is a positive integer, and P is an integer greater than 1, the each encoder group configured to:
- encode a part of bits in the second value, a group selection signal, and a symbol control input signal, the symbol control input signal corresponding to the each encoder group, the encoding using non-inversion encoding operators or inversion encoding operators to obtain one partial product, the group selection signal and the symbol control input signal being generated based on a part of bits in the first value, and the P groups of encoders performing encoding to obtain P partial products;
- and
- compress the P partial products using inversion compression operators to obtain two accumulated values, a sum of the two accumulated values comprising a product of the first value and the second value.
3 more elements
An operator circuit, comprising:
- a first transistor and a second transistor are coupled in parallel between a power supply terminal and a first node;
- a third transistor and a fourth transistor are coupled in parallel between the first node and a second node;
- a fifth transistor and a seventh transistor are coupled in series between the second node and a ground terminal;
- a sixth transistor and an eighth transistor are coupled in series between the second node and the ground terminal;
- control terminals of the third transistor and the fifth transistor are configured to receive a first input;
- control terminals of the first transistor and the sixth transistor are configured to receive a second input;
- control terminals of the fourth transistor and the seventh transistor are configured to receive a third input;
- control terminals of the second transistor and the eighth transistor are configured to receive a fourth input;
- a ninth transistor is coupled between an inversion of a fifth input and an output terminal, and a control terminal of the ninth transistor is coupled to the second node;
- a tenth transistor is coupled between the second node and the output terminal, and a control terminal of the tenth transistor is coupled to the inversion of the fifth input;
- an eleventh transistor and a thirteenth transistor are coupled in series between the output terminal and the ground terminal;
- a control terminal of the eleventh transistor is coupled to the second node;
- a control terminal of the thirteenth transistor is configured to receive the inversion of the fifth input;
- a twelfth transistor is coupled between the output terminal and the second node, and a control terminal of the twelfth transistor is configured to receive the fifth input;
- a fourteenth transistor and a fifteenth transistor are coupled in series between the power supply terminal and the ground terminal, and a series coupled node between the fourteenth transistor and the fifteenth transistor is coupled to the inversion of the fifth input;
- and
- control terminals of the fourteenth transistor and the fifteenth transistor are configured to receive the fifth input.
14 more elements
An operator circuit, comprising:
- a first transistor and a second transistor are coupled in parallel between a power supply terminal and a first node;
- a third transistor and a fourth transistor are coupled in parallel between the first node and a second node;
- a fifth transistor and a seventh transistor are coupled in series between the second node and a ground terminal;
- a sixth transistor and an eighth transistor are coupled in series between the second node and the ground terminal;
- control terminals of the third transistor and the fifth transistor are configured to receive a first input;
- control terminals of the first transistor and the sixth transistor are configured to receive a second input;
- control terminals of the fourth transistor and the seventh transistor are configured to receive a third input;
- control terminals of the second transistor and the eighth transistor are configured to receive a fourth input;
- a ninth transistor and a tenth transistor are coupled in series between the power supply terminal and an output terminal, a control terminal of the ninth transistor is coupled to an inversion of a fifth input, and a control terminal of the tenth transistor is coupled to the second node;
- an eleventh transistor is coupled between the second node and the output terminal, and a control terminal of the eleventh transistor is coupled to the fifth input;
- a twelfth transistor is coupled between the output terminal and the inversion of the fifth input, and a control terminal of the twelfth transistor is coupled to the second node;
- a thirteenth transistor is coupled between the output terminal and the second node, and a control terminal of the thirteenth transistor is coupled to the inversion of the fifth input;
- a fourteenth transistor and a fifteenth transistor are coupled in series between the power supply terminal and the ground terminal, and a series coupled node between the fourteenth transistor and the fifteenth transistor is coupled to the inversion of the fifth input;
- and
- control terminals of the fourteenth transistor and the fifteenth transistor are configured to receive the fifth input.
12 more elements
An operator circuit, comprising:
- a first transistor and a second transistor are coupled in parallel between a power supply terminal and a first node;
- a third transistor is coupled between the first node and a first output terminal;
- a fourth transistor is coupled between the first output terminal and a second node;
- a fifth transistor and a sixth transistor are coupled in parallel between the second node and a ground terminal;
- a seventh transistor is coupled between the power supply terminal and a third node;
- an eighth transistor is coupled between the third node and the first output terminal;
- a ninth transistor is coupled between the first output terminal and a fourth node;
- a tenth transistor is coupled between the fourth node and the ground terminal;
- an eleventh transistor and a twelfth transistor are coupled in series between the third node and a second output terminal;
- a thirteenth transistor and a fourteenth transistor are coupled in series between the second output terminal and the fourth node;
- a fifteenth transistor, a sixteenth transistor, and a seventeenth transistor are coupled in parallel between the power supply terminal and a fifth node;
- an eighteenth transistor is coupled between the fifth node and the second output terminal;
- a nineteenth transistor is coupled between the second output terminal and a sixth node;
- a twentieth transistor, a twenty-first transistor, and a twenty-second transistor are coupled in parallel between the sixth node and the ground terminal;
- control terminals of the third transistor, the fourth transistor, the twelfth transistor, the thirteenth transistor, the fifteenth transistor, and the twentieth transistor are configured to receive a first input;
- control terminals of the first transistor, the fifth transistor, the seventh transistor, the tenth transistor, the sixteenth transistor, and the twenty-first transistor are configured to receive a second input;
- control terminals of the second transistor, the sixth transistor, the eighth transistor, the ninth transistor, the eleventh transistor, the fourteenth transistor, the seventeenth transistor, and the twenty-second transistor are configured to receive a third input;
- and
- control terminals of the eighteenth transistor and the nineteenth transistor are coupled to the first output terminal.
16 more elements
An inversion compressor, comprising:
- W layers of inversion compressors, W being an integer greater than 1, the W layers of inversion compressors comprise a first layer of inversion compressors to a Wth layer of inversion compressors;
- wherein the first layer of inversion compressors are configured to compress each digit weight in a matrix of P partial products using inversion compression operators in a sequence from a low digit weight to a high digit weight until a quantity of remaining bits corresponding to the each digit weight are less than three, to obtain a first compressed matrix;
- an ith layer of inversion compressors are configured to compress the each digit weight in an (i−1)th compressed matrix using the inversion compression operators in a sequence from a low digit weight to a high digit weight until a quantity of remaining bits corresponding to the each digit weight are less than three, to obtain an ith compressed matrix, wherein a value of i ranges from 2 to W;
- and
- a Wth compressed matrix comprises two rows and each row corresponds to one accumulated value;
- wherein compression on the each digit weight by each layer of inversion compressors is performed for the three bits on the digit weight, and in the matrix of the P partial products each row comprises one partial product and each column comprises a plurality of bits corresponding to a same digit weight in the P partial products.
3 more elements
Dependencies are inferred from the claim text.