Gated tri-state inverter, and low power reduced area phase interpolator system including same, and method of operating same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsTsung-Che Lu, Chin-Ming Fu, Chih-Hsien Chang
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Abstract
A phase interpolating (PI) system includes: a PI stage configured to receive first and second clock signals and a multi-bit weighting signal, and generate an interpolated clock signal; and an amplifying stage configured to receive and amplify the interpolated clock signal, the amplifying stage including a capacitive component. The capacitive component is tunable to exhibit non-zero capacitances. The capacitive component has a Miller effect configuration resulting in a reduced footprint of the amplifying stage.
Claims19
A phase interpolating (PI) system comprising:
- a phase-interpolating (PI) stage configured to receive first and second clock signals and a multi-bit weighting signal, and generate an interpolated clock signal;
- and
- an amplifying stage configured to receive and amplify the interpolated clock signal, the amplifying stage including a capacitive component;
- the capacitive component being tunable to exhibit non-zero capacitances;
- and
- the capacitive component having a Miller effect configuration resulting in a reduced footprint of the amplifying stage.
A phase interpolating (PI) system comprising:
- a phase-interpolating (PI) stage configured to receive first and second clock signals and a multi-bit weighting signal, and generate an interpolated clock signal;
- and
- an amplifying stage configured to receive and amplify the interpolated clock signal, the amplifying stage including:
- an amplifier, an input of the amplifier being configured to receive an output of the PI stage, and an output of the amplifier representing an output of the amplifying stage;
- and
- a network of selectable, parallel connected capacitive paths coupled in a feedback arrangement between the input and output of the amplifier, the network representing a capacitive component that couples the output of the amplifier to the input of the amplifier;
- the network being tunable to exhibit non-zero capacitances;
- the network having a Miller effect configuration resulting in a reduced footprint of the amplifying stage;
- and
- the network of selectable, parallel connected capacitive paths including:
- a switchable first capacitive path represents a first capacitance;
- a switchable second capacitive path represents a second capacitance;
- and
- a switchable third capacitive path represents a third capacitance;
- the first capacitance being less than the second capacitance;
- and
- the second capacitance being less than the third capacitance.
A phase interpolating (PI) system comprising:
- a phase-interpolating (PI) stage configured to receive first and second clock signals and a multi-bit weighting signal, and generate an interpolated clock signal;
- and
- an amplifying stage configured to receive and amplify the interpolated clock signal, the amplifying stage including a capacitive component;
- the capacitive component being tunable to exhibit non-zero capacitances;
- and
- the capacitive component having a Miller effect configuration resulting in a reduced footprint of the amplifying stage;
- and
- the PI stage further being configured to avoid a pull-up/pull-down (PUPD) short-circuit situation by using the multi-bit weighting signal and a logical inverse thereof (multi-bit weighting_bar signal).
Dependencies are inferred from the claim text.