Integrated resistor network and method for fabricating the same

A temperature detecting system comprising:

• a current source coupled in series with a low range voltage-generating resistor network comprising:
• a voltage-generating-section including a resistor ladder having a first number (n) of first integrated resistors coupled in series between a top contact and a bottom contact, with one or more contacts coupled between adjacent individual integrated resistor, wherein n is a natural positive number greater than 2;
• and
• a current-path coupled in parallel with the voltage-generating-section, the current-path including n−1 second integrated resistors coupled in parallel with one another, each having a first terminal directly connected to the bottom contact, and a single third integrated resistor connected in series between second terminals of the second number of second integrated resistors and the top contact,
• wherein each of the first, second and third integrated resistors have substantially equal resistances, and a voltage developed across each of the first integrated resistors in the voltage-generating-section is VTOP-BOT/n, where VTOP-BOT is a voltage applied between the top contact and the bottom contact.

An integrated resistor network comprising:

• a resistor ladder including a first number (n) of first integrated resistors coupled in series between a top contact and a bottom contact, with one or more contacts coupled between two adjacent first integrated resistors, wherein n is a natural positive number greater than 2;
• and
• a current-path coupled in parallel with the resistor ladder, the current-path consisting of n−1 second integrated resistors coupled in parallel, and a single third integrated resistor coupled in series with the second number of second integrated resistors between the top contact and the bottom contact,
• wherein each of the first, second and third integrated resistors have substantially equal width, length, and a resistance of R, and
• wherein a voltage resolution of the voltage developed across each of the first integrated resistors is substantially equal to that developed across each integrated resistor of an n2 integrated resistor network comprising a total of n2 integrated resistors, and wherein a total capacitance of the integrated resistor network is reduced to a factor of 2n/n2 relative to that of the n2 integrated resistor network.