Adaptive control of non-overlapping drive signals

An electronic circuit comprising:

• a means for generating first drive pulses that are based on and delayed from first initial pulses;
• a means for generating second drive pulses that are based on and delayed from second initial pulses, wherein the first initial pulses do not overlap in time with the second initial pulses;
• a means for detecting a current flow in response to an on-time overlap of an on-time state of the first drive pulses with an on-time state of the second drive pulses;
• and
• a programmable delay circuit in a gate drive circuit that decreases the delay of the second drive pulses based on the current flow overlapping with one of the first initial pulses, and that increases the delay of the second drive pulses based on the current flow overlapping with one of the second initial pulses.

An electronic circuit comprising:

• a first current detection transistor that is driven by first drive pulses, wherein an array of first transistor segments comprises a first transistor segment and other first transistor segments, and the first current detection transistor comprises the first transistor segment;
• a second current detection transistor that is driven by second drive pulses, wherein an array of second transistor segments comprises a second transistor segment and other second transistor segments, the second current detection transistor comprises the second transistor segment, and a sample current is flowed through the first current detection transistor and the second current detection transistor in response to an on-time state of the first current detection transistor overlapping with an on-time state of the second current detection transistor;
• and
• a programmable delay circuit that reduces the sample current by shifting the second drive pulses based on a detection of the sample current through the first current detection transistor and the second current detection transistor.