US 11,855,206 B2Granted

Semiconductor device

AssigneesKabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation

InventorMasataka Ino

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Abstract

A semiconductor device includes first and second metal layers, a dielectric layer, first, second, and third semiconductor regions, a first control electrode, and a first electrode. The dielectric layer is located on the first metal layer. The second metal layer is located on the dielectric layer, and electrically connected with the first metal layer. The first semiconductor region is located on the second metal layer and electrically connected with the second metal layer. The second semiconductor region is located on the first semiconductor region. The third semiconductor region is located on the second semiconductor region. The first control electrode faces the second semiconductor region via a first insulating film. The first electrode is located on the third semiconductor region and the first control electrode, electrically connected with the third semiconductor region, and insulated from the first control electrode by a first insulating portion.

Claims15

Dependent claims

A semiconductor device, comprising:

a first metal layer;
a dielectric layer located on the first metal layer;
a second metal layer located on the dielectric layer, the second metal layer being electrically connected with the first metal layer;
a first semiconductor region located on the second metal layer and electrically connected with the second metal layer, the first semiconductor region being of a first conductivity type;
a second semiconductor region located on the first semiconductor region, the second semiconductor region being of a second conductivity type;
a third semiconductor region located on the second semiconductor region, the third semiconductor region being of the first conductivity type;
a first control electrode facing the second semiconductor region via a first insulating film;
and
a first electrode located on the third semiconductor region and the first control electrode, the first electrode being electrically connected with the third semiconductor region, the first electrode being insulated from the first control electrode by a first insulating portion.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/464,620Filed 1 Sep 2021
Priority: JP 2021-02398518 Feb 2021
Published: US 2022/0262952 A118 Aug 2022
Granted: 26 Dec 2023
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10D 30/668
Vertical dmos [vdmos] fets: having trench gate electrodes, e.g. UMOS transistors
H10D 30/791
Insulated-gate field-effect transistors [IGFET]: arrangements for exerting mechanical stress on the crystal lattice of the channel regions
H10D 30/645
Double-diffused metal-oxide semiconductor [DMOS] FETs: bidirectional devices
H10D 64/252
Source or drain electrodes for field-effect devices: for vertical or pseudo-vertical devices