Methods of designing and fabricating a semiconductor device based on determining a least common multiple between select layout pitches

A method of designing a semiconductor device, the method comprising:

• performing a simulation a number of times, the simulation including,
• holding a gate pitch of a plurality of gate wiring patterns constant,
• varying a first pitch of first wiring patterns of a plurality of first-direction wiring patterns that extend in a first direction,
• varying a second pitch of second wiring patterns of the plurality of first-direction wiring patterns that extend in the first direction, and
• varying a third pitch of third wiring patterns of the plurality of first-direction wiring patterns that extend in the first direction;
• for each of the number of times, calculating a calculated least common multiple of the gate pitch, the first pitch, the second pitch, and the third pitch;
• determining a determined least common multiple from among the calculated least common multiples;
• and
• designing a plurality of layers based on the determined least common multiple.