Memory device, testing method and using method thereof, and memory system
AssigneeChangxin Memory Technologies, Inc.
InventorShu-Liang Ning
Life of this patent
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Abstract
A memory device includes: a plurality of channels, each including a memory cell array, the memory cell array including a normal cell array, the normal cell array including normal memory cells, and each of the normal memory cells being a volatile memory cell; a testing control circuit, configured to control testing of the normal cell array in the plurality of channels in response to a testing instruction, and to determine an access address of a normal memory cell failing the testing in the normal cell array in the plurality of channels to be a failure address; and a non-volatile memory cell array which includes a plurality of non-volatile memory cells and is configured to receive and store the failure address from the testing control circuit.
Claims19
A memory device, comprising:
- a plurality of channels, each channel comprising a memory cell array, the memory cell array comprising a normal cell array, the normal cell array comprising normal memory cells, and each of the normal memory cells being a volatile memory cell;
- a testing control circuit, configured to control testing of the normal cell array in each of the plurality of channels in response to a testing instruction and to determine an access address of a normal memory cell failing the testing in the normal cell array in each of the plurality of channels to be a failure address;
- and
- a non-volatile memory cell array, configured to receive and store the failure address from the testing control circuit;
- wherein each of the channels further comprises a latch block, wherein the non-volatile memory cell array further comprises:
- a scan host, configured to, responsive to the memory device being powered on, transfer the failure address in the non-volatile memory cell array to the latch block of the channel corresponding to the failure address.
A method for testing a memory device, wherein the memory device comprises a plurality of channels and a non-volatile memory cell array, each of the channels comprises a memory cell array and a latch block, the memory cell array comprises a normal cell array, the normal cell array comprises normal memory cells, each of the normal memory cell is a volatile memory cell, and the non-volatile memory cell array comprises a plurality of non-volatile memory cells, wherein the method comprises:
- receiving a testing instruction;
- controlling testing of the normal cell array in the plurality of channels according to the testing instruction and determining an access address of a normal memory cell failing the testing in the normal cell array in the plurality of channels to be a failure address;
- and
- sending and storing the failure address to the non-volatile memory cell array,
- wherein responsive to the memory device being powered on, the failure address in the non-volatile memory cell array is transferred to the latch block of the channel corresponding to the failure address.
A method for using a memory device, wherein the memory device comprises a plurality of channels and a non-volatile memory cell array, each of the channels comprises a memory cell array and a latch block, the memory cell array comprises a normal cell array, the normal cell array comprises normal memory cells, each of the normal memory cells is a volatile memory cell, the non-volatile memory cell array comprises a plurality of non-volatile memory cells, and the non-volatile memory cell array is configured to store a failure address indicating an access address of a normal memory cell failing the testing in the normal cell array in the plurality of channels, wherein the method comprises:
- responsive to the memory device being powered on, transferring the failure address in the non-volatile memory cell array to the latch block of the channel corresponding to the failure address.
Dependencies are inferred from the claim text.