Anti-fuse memory cell state detection circuit and memory
AssigneeChangxin Memory Technologies, Inc.
InventorRumin Ji
Life of this patent
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Abstract
A state detection circuit of an anti-fuse memory cell includes a first switching element, having a first end connected to a power supply, a second end connected to a first node, and a control end connected to a controller; an anti-fuse memory cell array including a plurality of anti-fuse memory cell sub-arrays, bit lines of the plurality of anti-fuse memory cell sub-arrays being all connected to the first node, and word lines of the plurality of anti-fuse memory cell sub-arrays being all connected to the controller; and a comparator, having a first input end connected to the first node, and a second input end connected to a reference voltage.
Claims11
A state detection circuit of an anti-fuse memory cell, comprising:
- a first switching element, having a first end connected to a power supply, a second end connected to a first node, and a control end connected to a controller;
- an anti-fuse memory cell array comprising a plurality of anti-fuse memory cell sub-arrays, bit lines of the plurality of anti-fuse memory cell sub-arrays being all connected to the first node, and word lines of the plurality of anti-fuse memory cell sub-arrays being all connected to the controller;
- and
- a comparator, having a first input end connected to the first node, and a second input end connected to a reference voltage;
- wherein the anti-fuse memory cell sub-array comprises a plurality of anti-fuse memory cells;
- and the controller is configured to detect states of the plurality of anti-fuse memory cells one by one by switching on or off the first switching element,
- wherein the controller is further configured to:
- output a first control signal at a first time point to switch on the first switching element;
- output a second control signal at a second time point to switch off the first switching element, and output a third control signal to switch on one of the plurality of anti-fuse memory cells;
- and
- acquire an output signal of the comparator at a third time point;
- wherein the third time point is later than the second time point, and the second time point is later than the first time point, and
- wherein the third time point is determined according to following approaches:
- acquiring a maximum resistance of the anti-fuse memory cell after being broken down and a minimum resistance of the anti-fuse memory cell without being broken down;
- determining a first voltage change curve and a second voltage change curve of the first node according to the power supply, the maximum resistance and the minimum resistance;
- and
- taking a time point where a difference value between the first voltage change curve and the second voltage change curve is the largest as the third time point.
Dependencies are inferred from the claim text.