Semiconductor memory structure and fabrication method thereof

A method of forming a semiconductor memory structure, comprising:

• providing a substrate having thereon a transistor forming region and a capacitor forming region in proximity to the transistor forming region;
• forming a transistor on the substrate within the transistor forming region;
• forming a capacitor on the substrate within the capacitor forming region and electrically coupled to a terminal of the transistor;
• forming a first interlayer dielectric layer covering the transistor forming region and the capacitor forming region, wherein the first interlayer dielectric layer surrounds a metal gate of the transistor and a bottom plate of the capacitor;
• and
• forming a cap layer on the first interlayer dielectric layer, wherein the cap layer has a first thickness within the transistor forming region and a second thickness within the capacitor forming region, wherein the first thickness is greater than the second thickness, wherein the cap layer within the capacitor forming region acts as a capacitor dielectric layer of the capacitor.