Transmission apparatus
AssigneePanasonic Intellectual Property Corporation of America
InventorsYutaka Murakami, Shutai Okamura
Life of this patent
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Abstract
Disclosed are an encoder, a transmission device, and an encoding method with which the transmission amount is reduced and a deterioration in transmission efficiency is suppressed while improving reception quality when QC-LDPC or a like block encoding is used. A puncture pattern setting unit (620) searches for a puncture pattern for each integral multiple of the number of columns or for each divisor of the number of columns of a sub block matrix that forms a check matrix (H) of a QC-LDPC code, and a puncture unit (data reduction unit) (630) switches the puncture pattern for each integral multiple of the number of columns or for each divisor of the number of columns of the sub block matrix that forms the check matrix of the QC-LDPC code.
Claims6
A transmission apparatus comprising:
- encoding circuitry which, in operation, performs a low density parity check (LDPC) encoding on an information bit sequence to generate a first codeword sequence s comprising the information bit sequence and a parity bit sequence, the first codeword sequence s satisfying Equation 1,
- Hs=0 (Equation 1)
- where a parity check matrix H has z×mb rows and z×nb columns configured by arranging submatrices of z rows and z columns in mb rows and nb columns;
- removal circuitry which, in operation, removes one or more sets of consecutive bits from the parity bit sequence to generate a second codeword sequence, using a removing pattern indicative of which of the one or more sets of consecutive bits are to be removed;
- modulation circuitry which, in operation, modulates the second codeword sequence to generate a modulated symbol sequence;
- and
- transmission circuitry which, in operation, transmits a transmission frame including the modulated symbol sequence.
A transmission method comprising:
- performing a low density parity check (LDPC) encoding on an information bit sequence to generate a first codeword sequence s comprising the information bit sequence and a parity bit sequence, the first codeword sequence s satisfying Equation 3,
- Hs=0 (Equation 3)
- where a parity check matrix H has z×mb rows and z×nb columns configured by arranging submatrices of z rows and z columns in mb rows and nb columns;
- removing one or more sets of consecutive bits from the parity bit sequence to generate a second codeword sequence, using a removing pattern indicative of which of the one or more sets of consecutive bits are to be removed;
- modulating the second codeword sequence to generate a modulated symbol sequence;
- and
- transmitting a transmission frame including the modulated symbol sequence.
Dependencies are inferred from the claim text.