Method of forming lateral pn junctions in III-nitrides using p-type and n-type co-doping and selective p-type activation and deactivation
AssigneeOhio State Innovation Foundation
InventorsSiddharth Rajan, Mohammad Wahidur Rahman, Hareesh Chandrasekar
Life of this patent
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Abstract
Methods are provided of selectively obtaining n-type and p-type regions from the same III-Nitride layer deposited on a substrate without using diffusion or ion-implantation techniques. The III-Nitride layer is co-doped simultaneously with n-type and p-type dopants, with p-type dopant concentration higher than n-type dopant to generate p-n junctions. The methods rely on obtaining activated p-type dopants only in selected regions to generate p-type layers, whereas the rest of the regions effectively behave as an n-type layer by having deactivated p-type dopant atoms.
Claims13
A semiconductor structure comprising:
- a first region doped with a p-type dopant, an n-type dopant, and a passivating species, such that the passivating species deactivates an acceptor, and an active p-type dopant concentration is less than an active donor concentration (ND), thus creating a n-type layer;
- a second region adjacent the first region, wherein the second region is doped with the p-type dopant, the n-type dopant, and wherein the concentration of the passivating species is lower than the first region so that a p-type dopant concentration is higher than the active donor concentration (ND), thus creating a p-type layer;
- and
- an overlayer over the first region and the second region, wherein the overlayer is an out diffusion barrier for the passivating species.
A method for fabricating a semiconductor structure comprising:
- The
- depositing an overlayer on a sample surface of the semiconductor structure which acts as an out-diffusion barrier for a passivating species;
- patterning the sample surface to retain the deposited overlayer in selected areas of the sample surface;
- and
- performing activation treatment of the sample surface to obtain p-regions in areas without the overlayer and n-type regions in areas of the sample surface underneath the overlayer.
A method for fabricating a semiconductor structure comprising:
- depositing an overlayer on a sample surface of a semiconductor surface which acts as in-diffusion barrier to a passivating species;
- patterning the sample surface to retain the deposited overlayer in selected areas of the sample surface;
- and
- subjecting the sample surface to p-type deactivation treatment to obtain n-regions in areas without the overlayer and p-type regions in areas of the sample surface underneath the overlayer.
Dependencies are inferred from the claim text.