Semiconductor package and manufacturing method thereof

A method, comprising:

• providing a semiconductor die;
• laterally encapsulating the semiconductor die with a first encapsulant;
• forming redistribution sublayers including a dielectric layer and a metallic wiring over the semiconductor die and the first encapsulant;
• forming a redistribution wiring on the dielectric layer and electrically connected to the metallic wiring;
• forming a conductive via on the redistribution wiring;
• forming a second encapsulant wrapping around the conductive via and the redistribution wiring;
• and
• forming an under-ball metallurgy (UBM) pattern on the conductive via, wherein a lower surface of the UBM pattern is coplanar with upper surfaces of the second encapsulant and the conductive via.

A semiconductor package, comprising:

• a semiconductor die;
• and
• a redistribution structure, disposed on the semiconductor die and electrically connected to the semiconductor die, the redistribution structure comprising:
• redistribution sublayers including a dielectric layer and a metallic wiring;
• and
• a redistribution wiring disposed on the dielectric layer and connected to the metallic wiring;
• a plurality of conductive vias disposed on the redistribution wiring;
• and
• an encapsulant laterally encapsulating the redistribution wiring and the conductive via;
• and
• a plurality of under-ball metallurgy (UBM) patterns respectively disposed on the conductive vias, wherein a lower surface each of the UBM patterns is coplanar with upper surfaces of the encapsulant and the corresponding conductive via.