Precise data tuning method and apparatus for analog neural memory in an artificial neural network

A neuron output circuit comprising:

• an adjustable capacitor comprising a first terminal coupled to a voltage source and a second terminal providing an output voltage for the neuron output circuit;
• a control transistor comprising a first terminal, a second terminal, and a gate receiving a control signal;
• a first switch selectively coupled between the first terminal and the second terminal of the adjustable capacitor;
• a second switch selectively coupled between the second terminal of the adjustable capacitor and the first terminal of the control transistor;
• and
• an adjustable current source coupled between the second terminal of the control transistor and ground, wherein the adjustable current source generates a scaled current in response to a neuron current and the control signal.

A neuron output circuit comprising:

• an adjustable capacitor comprising a first terminal coupled to a voltage source and a second terminal providing an output voltage for the neuron output circuit;
• a control transistor comprising a first terminal, a second terminal, and a gate receiving a control signal;
• a switch selectively coupled between the second terminal of the adjustable capacitor and the first terminal of the control transistor;
• and
• an adjustable current source coupled between the second terminal of the control transistor and ground, wherein the adjustable current source generates a scaled current in response to a neuron current and the control signal.

A neuron output circuit comprising:

• an adjustable capacitor comprising a first terminal and a second terminal, the first terminal providing an output voltage for the neuron output circuit;
• a control transistor comprising a first terminal, a second terminal, and a gate receiving a control signal;
• a first switch selectively coupled between the first terminal of the adjustable capacitor and the first terminal of the control transistor;
• and
• an adjustable current source coupled between the second terminal of the control transistor and ground, wherein the adjustable current source generates a scaled current in response to a neuron current and the control signal.

A neuron output circuit comprising:

• a first operational amplifier comprising an inverting input, a non-inverting input, and an output;
• a second operational amplifier comprising an inverting input, a non-inverting input, and an output;
• a first adjustable current source coupled between the inverting input of the first operational amplifier and ground to generate a first scaled current in response to a first neuron current and a first control signal;
• a second adjustable current source coupled between the inverting input of the second operational amplifier and ground to generate a second scaled current in response to a second neuron current and a second control signal;
• a first adjustable resistor coupled between the output of the first operational amplifier and the inverting input of the first operational amplifier;
• a second adjustable resistor coupled between the output of the second operational amplifier and the inverting input of the second operational amplifier;
• and
• a third adjustable resistor coupled between the output of the first operational amplifier and the inverting input of the second operational amplifier.

A neuron output circuit comprising:

• a first operational amplifier comprising an inverting input, a non-inverting input, and an output;
• a second operational amplifier comprising an inverting input, a non-inverting input, and an output;
• a first adjustable current source coupled between the inverting input of the first operational amplifier and ground to generate a first scaled current in response to a first neuron current and a first control signal;
• a second adjustable current source coupled between the inverting input of the second operational amplifier and ground to generate a second scaled current in response to a second neuron current and a second control signal;
• a first switch coupled between the inverting input and the output of the first operational amplifier;
• a second switch coupled between the inverting input and the output of the second operational amplifier;
• a first adjustable capacitor coupled between the inverting input and the output of the first operational amplifier;
• a second adjustable capacitor coupled between the inverting input and the output of the second operational amplifier;
• and
• a third adjustable capacitor coupled between the output of the first operational amplifier and the inverting input of the second operational amplifier.