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US 11,846,672 B2Granted
Method and device for testing system-on-chip, electronic device using method, and computer readable storage medium
AssigneeHon Hai Precision Industry Co., Ltd.
InventorJun-Kui Huang
Life of this patent
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Abstract
A method for testing systems on a chip during manufacture obtains basic function information of intellectual property cores and relevant information of network on chip and generates one or more test names according to the basic function information, and the relevant information of the network on chip. The method invokes a pre-prepared integral script to construct a running environment configured to invoke basic function scripts of to-be-tested intellectual property cores one by one, according to each of the test names which are generated. The method also generates the results of testing. A related electronic device and a non-transitory storage medium are also disclosed.
Claims17
A method for applying tests comprising:
- obtaining basic function information of a plurality of intellectual property cores and relevant information of a network on chip;
- generating one or more test names according to the basic function information of the intellectual property cores and the relevant information of the network on chip;
- invoking a pre-written integral script to construct a running environment configured to invoke a plurality of pre-written basic function scripts of to-be-tested intellectual property cores one by one, according to each of the one or more test names which are generated;
- and
- generating results of testing;
- wherein a method of obtaining the basic function information of a plurality of intellectual property cores and the relevant information of the network on chip comprises:
- obtaining the basic function information of the intellectual property cores and a data transmission path in the network on chip;
- wherein a method of generating the one or more test names according to the basic function information of the intellectual property cores and the relevant information of the network on chip comprises:
- generating the one or more test names according to the basic function information of the intellectual property cores and the data transmission path in the network on chip, each of the one or more test names comprising a to-be-tested intellectual property core which executes a data writing operation, a to-be-tested intellectual property core which executes a data reading operation, a to-be-verified and to-be-tested intellectual property core, and one or more manners of data transmission between the to-be-tested intellectual property cores.
6 more elements
An electronic device comprising:
- a storage device;
- at least one processor;
- and
- the storage device storing one or more programs, which when executed by the at least one processor, cause the at least one processor to:
- obtain basic function information of a plurality of intellectual property cores and relevant information of a network on chip;
- generate one or more test names according to the basic function information of the intellectual property cores and the relevant information of the network on chip;
- invoke a pre-written integral script to construct a running environment configured to invoke a plurality of pre-written basic function scripts of to-be-tested intellectual property cores one by one, according to each of the one or more test names which are generated;
- generate results of testing;
- further causing the at least one processor to:
- obtain the basic function information of the intellectual property cores and a data transmission path in the network on chip;
- generate the one or more test names according to the basic function information of the intellectual property cores and the data transmission path in the network on chip, each of the one or more test names comprising a to-be-tested intellectual property core which executes a data writing operation, a to-be-tested intellectual property core which executes a data reading operation, a to-be-verified and to-be-tested intellectual property core, and one or more manners of data transmission between the to-be-tested intellectual property cores.
8 more elements
A non-transitory storage medium storing a set of commands, when the commands being executed by at least one processor of an electronic device, causing the at least one processor to:
- obtain basic function information of a plurality of intellectual property cores and relevant information of a network on chip;
- generate one or more test names according to the basic function information of the intellectual property cores and the relevant information of the network on chip;
- invoke a pre-written integral script to construct a running environment configured to invoke a plurality of pre-written basic function scripts of to-be-tested intellectual property cores one by one, according to each of the one or more test names which are generated;
- generate results of testing;
- further causing the at least one processor to:
- obtain the basic function information of the intellectual property cores and a data transmission path in the network on chip;
- generate the one or more test names according to the basic function information of the intellectual property cores and the data transmission path in the network on chip, each of the one or more test names comprising a to-be-tested intellectual property core which executes a data writing operation, a to-be-tested intellectual property core which executes a data reading operation, a to-be-verified and to-be-tested intellectual property core, and one or more manners of data transmission between the to-be-tested intellectual property cores.
4 more elements
Dependencies are inferred from the claim text.