Latched comparator circuitry with reduced clock feedthrough

A differential circuit comprising:

• a latch having a pair of cross-coupled inverting circuits, wherein a first inverting circuit in the pair of cross-coupled inverting circuit includes a first n-type transistor and a first p-type transistor, and wherein a second inverting circuit in the pair of cross-coupled inverting circuits includes a second n-type transistor and a second p-type transistor;
• and
• a first input transistor coupled between the first n-type transistor and the first p-type transistor in the first inverting circuit;
• a second input transistor coupled between the second n-type transistor and the second p-type transistor in the second inverting circuit;
• and
• a current pulse generator coupled to source terminals of the first and second n-type transistors and configured to receive a clock signal, wherein the current pulse generator is configured to output a current pulse that is less than 10% of a period of the clock signal.

A comparator comprising:

• a first input transistor having a gate terminal configured to receive an input signal;
• a second input transistor having a gate terminal configured to receive the input signal;
• a first pull-down transistor having a drain terminal coupled to a source terminal of the first input transistor;
• a second pull-down transistor having a drain terminal coupled to a source terminal of the second input transistor and having a source terminal coupled to a source terminal of the first pull-down transistor;
• and
• a pulse generator coupled to the source terminals of the first and second pull-down transistors and configured to receive a clock signal having a first duty cycle, wherein the pulse generator is configured to output a pulse having a second duty cycle that is at least five times shorter than the first duty cycle.