Semiconductor arrangement and method for manufacturing the same

A method of manufacturing a semiconductor arrangement, comprising:

• forming a fin on a bulk semiconductor substrate;
• forming a first isolation section in a region of the bulk semiconductor substrate at the bottom of the fin, wherein the first isolation section comprises at least one of an insulation layer, a pn junction isolation, or a doped semiconductor isolation;
• forming a dummy gate structure intersecting the fin in the region on the bulk semiconductor substrate, and a first gate structure and a second gate structure intersecting the fin on opposite sides of the dummy gate structure;
• forming a first gate spacer, a second gate spacer, and a dummy gate spacer on sidewalls of the first gate structure, the second gate structure, and the dummy gate structure, respectively;
• forming a trench self-aligned to a space defined by the dummy gate spacer, wherein the trench extends to the first isolation section;
• and
• filling the trench with a dielectric material to form a second isolation section.