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US 11,841,823 B2Granted
Connectivity in coarse grained reconfigurable architecture
AssigneeMicron Technology, Inc.
InventorsBryan Hornung, Tony M. Brewer
Life of this patent
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Abstract
A reconfigurable compute fabric can include multiple nodes, and each node can include multiple tiles with respective processing and storage elements. The tiles can be arranged in an array or grid and can be communicatively coupled. In an example, the tiles can be arranged in a one-dimensional array and each tile can be coupled to its respective adjacent neighbor tiles using a direct bus coupling. Each tile can be further coupled to at least one non-adjacent neighbor tile that is one tile, or device space, away using a passthrough bus. The passthrough bus can extend through intervening tiles.
Claims20
A system comprising:
- multiple memory-compute nodes coupled to provide a reconfigurable compute fabric, wherein each of the nodes comprises a hybrid threading processor and hybrid threading fabric, and wherein the hybrid threading fabric of each node comprises multiple memory-compute tiles and each of the memory-compute tiles includes respective processing and storage elements;
- and
- a first memory-compute tile of a first node of the multiple memory-compute nodes, wherein the first memory-compute tile comprises:
- first tile inputs coupled to respective outputs of second and third memory-compute tiles of the first node, wherein the first tile inputs are coupled to processing or storage elements on the first tile;
- first tile outputs coupled to respective inputs of the second and third memory-compute tiles of the first node, wherein the first tile outputs are coupled to the processing element on the first tile;
- and
- a passthrough channel configured to communicate information between the second and third memory-compute tiles.
4 more elements
A system comprising:
- multiple memory-compute nodes coupled to provide a reconfigurable compute fabric, wherein each of the nodes comprises a hybrid threading processor and hybrid threading fabric, and wherein the hybrid threading fabric of each node comprises multiple memory-compute tiles and each of the memory-compute tiles includes respective processing and storage elements;
- and
- a first node of the multiple memory-compute nodes, the first node comprising:
- a first memory interface;
- and
- a first group of memory-compute tiles, wherein each of the memory-compute tiles in the first group is coupled, using a synchronous compute fabric, with at least two neighboring memory-compute tiles in the first group, and wherein each of the memory-compute tiles in the first group is coupled, using an asynchronous compute fabric and the first memory interface, with at least one non-neighboring memory-compute tile in the first group of memory-compute tiles.
3 more elements
A method comprising:
- receiving first data for a compute thread at a memory interface of a first node of a memory-compute system, wherein the memory interface is configured to receive the first data via an asynchronous compute fabric of the system;
- and
- at a first memory-compute tile of a plurality of memory-compute tiles in the first node of the system, initiating a synchronous thread portion of the compute thread;
- executing operations comprising the synchronous thread using the first memory-compute tile and at least a second memory-compute tile of the plurality of memory compute tiles, wherein executing the operations comprises communicating data between the first and second memory-compute tiles using a portion of a synchronous compute fabric that couples the plurality of memory-compute tiles;
- wherein each of the plurality of memory-compute tiles is directly communicatively coupled to two or more other tiles in the first node using a respective portion of the synchronous compute fabric, and wherein each of the plurality of memory-compute tiles is coupled to all of the other tiles in the first node using a respective portion of the asynchronous compute fabric.
2 more elements
Dependencies are inferred from the claim text.