Memory interface for a multi-threaded, self-scheduling reconfigurable computing fabric

A method of interfacing between a memory circuit and a plurality of configurable circuits, the memory circuit coupleable to a first interconnection network for transmission of a plurality of memory store data request packets to the memory circuit and for reception of a plurality of memory load data request packets from the memory circuit, and the plurality of configurable circuits coupleable to a second, asynchronous packet network for data packet communication for reception of a plurality of load requests and a plurality of store requests, the method comprising:

• storing a plurality of tables in a plurality of registers, the plurality of tables comprising a memory request table, a memory request identifier table, a memory response table, a memory data message table, and a memory response buffer;
• using a state machine circuit coupled to the plurality of registers, receiving a load request over the second, asynchronous packet network, and in response to the load request, obtaining a first memory request identifier from the load request, storing the first memory request identifier in the memory request identifier table, generating one or more memory load request data packets having the memory request identifier for transmission to the memory circuit, and storing load request information in the memory request table;
• and
• storing, in a plurality of queues coupled to the state machine circuit, one or more data packets for transmission on the first interconnection network or on the second, asynchronous packet network.

A system comprising a memory interface circuit and a plurality of configurable circuits, the memory interface circuit coupleable to a first interconnection network to transmit a plurality of memory store data request packets to a memory circuit and to receive a plurality of memory load data request packets from the memory circuit, and coupleable to a second, asynchronous packet network for data packet communication with the plurality of configurable circuits to receive a plurality of load requests and a plurality of store requests, the memory interface circuit comprising:

• a plurality of registers adapted to store a plurality of tables, the plurality of tables comprising a memory request table, a memory request identifier table, a memory response table, a memory data message table, and a memory response buffer;
• a state machine circuit coupled to the plurality of registers, the state machine circuit adapted to receive a load request over the second, asynchronous packet network, and in response to the load request, to obtain a first memory request identifier from the load request, to store the first memory request identifier in the memory request identifier table, to generate one or more memory load request data packets having the memory request identifier for transmission to the memory circuit, and to store load request information in the memory request table;
• and
• a plurality of queues coupled to the state machine circuit, the plurality of queues storing one or more data packets for transmission on the first interconnection network or on the second, asynchronous packet network;
• wherein the state machine circuit is further adapted to receive a load response data packet over the first interconnection network, and in response to the load response data packet, to store received data from the load response data packet in the memory response buffer and to index the received data in the memory response buffer by the first memory request identifier;
• and
• wherein the state machine circuit is further adapted to receive a store request over the second, asynchronous packet network, and in response to the store request, to obtain a second memory request identifier from the store request, to store the second memory request identifier in the memory request identifier table, and to generate one or more memory store request data packets for transmission on the first interconnection network to the memory circuit.