Error bounded multiplication by invariant rationals
AssigneeImagination Technologies Limited
InventorTheo Alan Drane
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Abstract
A hardware logic representation of a circuit to implement an operation to perform multiplication by an invariant rational is generated by truncating an infinite single summation array (which is represented in a finite way). The truncation is performed by identifying a repeating section and then discarding all but a finite number of the repeating sections whilst still satisfying a defined error bound. To further reduce the size of the summation array, the binary representation of the invariant rational is converted into canonical signed digit notation prior to creating the finite representation of the infinite array.
Claims13
A method of synthesizing a representation of a hardware logic multiplier configured to multiply an input value by a predetermined invariant rational that satisfies a defined error bound, wherein the method is performed by at least one processor, and the method comprising, by at least one processor:
- truncating a binary expansion of the predetermined invariant rational;
- converting the truncated binary expansion into canonical signed digit notation and expanding the canonical signed digit representation into a finite representation of an infinite expansion;
- generating a truncated single summation array from the infinite expansion by discarding one or more repeating sections of the array based upon the defined error bound;
- and
- synthesizing the representation of the hardware logic multiplier using said truncated single summation array.
A non-transitory computer readable storage medium having stored thereon computer executable instructions to synthesize a representation of a hardware logic multiplier, the computer executable instructions being arranged, when executed by a processor, to cause the processor to:
- truncate a binary expansion of a predetermined invariant rational, convert the truncated binary expansion into canonical signed digit notation and expand the canonical signed digit representation into a finite representation of an infinite expansion;
- generate a truncated single summation array from the infinite expansion by discarding one or more repeating sections of the array based upon a defined error bound;
- and
- synthesize the representation of the hardware logic multiplier using said truncated single summation array.
A hardware logic multiplier configured to multiply an input value by a predetermined invariant rational that satisfies a defined error bound, wherein the hardware logic multiplier is synthesized using a process comprising:
- truncating a binary expansion of the predetermined invariant rational;
- converting the truncated binary expansion into canonical signed digit notation and expanding the canonical signed digit representation into a finite representation of an infinite expansion;
- generating a truncated single summation array from the infinite expansion by discarding one or more repeating sections of the array based upon the defined error bound;
- and
- synthesizing the hardware logic multiplier using said truncated single summation array.
Dependencies are inferred from the claim text.