Demand based dynamic creation of data analytics query accelerators

A method for processing queries comprising:

• splitting a query into sub-queries;
• mapping the sub-queries to respective sets of filter properties;
• mapping the sets of filter properties to respective reconfiguration bitstreams;
• and
• configuring a plurality of filters within a field programable gate array (FPGA) according to respective ones of the respective reconfiguration bitstreams, wherein each filter is formed in a respective reconfigurable region of the FPGA, and wherein the reconfiguration bitstreams are received from a source external to the FPGA, routed to appropriate ones of the reconfigurable regions, and contains configuration information for implementing logical circuits using FPGA resources,
• wherein each filter comprises a plurality of partition pins having fixed physical locations and providing interfaces between the reconfigurable region of the filter and a static region of the FPGA, and for each filter the partition pins comprise a configuration interface partition pin corresponding to a configuration interface for receiving at least one of the reconfiguration bitstreams, wherein the configuration interface partition pin is dedicated to receiving at least one of the reconfiguration bitstreams.

A system for processing queries comprising:

• a driver for receiving a query and for controlling splitting the query into a plurality of sub-queries, mapping the sub-queries to respective sets of filter properties and mapping the sets of filter properties to respective reconfiguration bitstreams, generating an accelerator generation recipe based on the mapping of the sub-queries and the mapping of the sets of filter properties, and accessing one or more control status registers (CSRs) based on the accelerator generation recipe;
• and
• a query accelerator comprising
• a plurality of reconfigurable regions,
• a static region including a controller operable to receive one or more control status register (CSR) values from the driver and acquire the plurality of reconfiguration bitstreams based on the received CSR values, the reconfiguration bitstreams respectively corresponding to the reconfigurable regions, and the reconfiguration bitstreams specifying formation of respective filters in the reconfigurable regions, being received from a source external to the query accelerator and routed to appropriate ones of the reconfigurable regions, and containing configuration information for implementing logical circuits using query accelerator resources,
• each filter comprising
• one or more registers for controlling and monitoring operation of the filter,
• a memory for temporary storage in the filter,
• filter logic,
• an input stream interface for receiving data to be filtered,
• a filtered output stream interface for providing a result of operation of the filter, and
• a plurality of partition pins having fixed physical locations and providing interfaces between the reconfigurable region of the filter and the static region, the partition pins comprising a configuration interface partition pin corresponding to a configuration interface for receiving at least one of the reconfiguration bitstreams, wherein the configuration interface partition pin is dedicated to receiving at least one of the reconfiguration bitstreams.