Localized NoC switching interconnect for high bandwidth interfaces

An integrated circuit, comprising:

• a first hardware circuit;
• a second hardware circuit;
• and
• a network on chip (NoC) providing connectivity between the first and second hardware circuits, the NoC comprising:
• a sparse network coupled to the first hardware circuit;
• and
• a non-blocking network coupled to the second hardware circuit, wherein the non-blocking network provides a localized interface between the sparse network and the second hardware circuit.

A method, comprising:

• providing a NoC that comprises a sparse network and a non-blocking network;
• receiving data from a first hardware entity at the sparse network in the NoC, wherein an intended destination of the data is a second hardware entity connected to the non-blocking network;
• transmitting the data through the sparse network to the non-blocking network;
• and
• transmitting the data through the non-blocking network to the second hardware entity, wherein the non-blocking network provides a localized interface between the sparse network and the second hardware entity.