Link training scheme for high-speed serializer/deserializer

A method, comprising:

• providing, in a first component of an information handling system, a transmitter for a high-speed serial data interface;
• providing, in a second component of the information handling system, a receiver for the high-speed serial data interface, the receiver including a first equalization stage and a decision feedback equalization (DFE) stage, the first equalization stage having a first input to provide a first fine scale adjustment to the first equalization stage and a second input to scale the first fine scale adjustment in one of a first low equalization state and a first high equalization state, and the DFE stage having a plurality of tap inputs;
• providing, by the first component in a training mode for the high-speed serial data interface, a plurality of training runs on the high-speed serial data interface;
• receiving, by the second component in the training mode, the training runs;
• providing, for each training run, a fine adjustment to the first input and a set of tap settings for each tap input;
• determining whether or not a variation in the tap settings for the training runs is greater than a predetermined variation value;
• and
• when the variation is greater than the predetermined variation value, setting the second input to configure the first equalization stage from the first low equalization state to the first high equalization state.

An information handling system, comprising:

• a first component including a transmitter for a high-speed serial data interface;
• and
• a second component including a receiver for the high-speed serial data interface, the receiver including an automatic gain control (AGC) stage, a continuous-time linear equalization (CTLE) stage, and a decision feedback equalization (DFE) stage, the AGC stage having a first input to configure the AGC stage in one of a low gain state and a high gain state, the CTLE stage having a second input to configure the CTLE stage in one of a low attenuation state and a high attenuation state, and the DFE stage having a plurality of tap inputs;
• wherein:
• the first component is configured in a training mode for the high-speed serial data interface to provide a plurality of training runs on the high-speed serial data interface;
• and
• the second component is configured in the training mode to receive the training runs, to provide for each training run a set of tap settings for each tap input, to determine whether or not a variation in the tap settings for the training runs is greater than a predetermined variation value, and, when the variation is greater than the predetermined variation value, to 1) set the first input to configure the AGC stage from the low gain state to the high gain state, and 2) set the second input to configure the CTLE stage from the low attenuation state to the high attenuation state.