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US 11,831,341 B2Granted
Data compressor logic circuit
AssigneeArm Limited
InventorsShardendu Shekhar, Andy Wangkun Chen, Yew Keong Chong
Life of this patent
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Abstract
A compressor includes a logic circuit having transistors of a first channel type to receive a plurality of bit signals, and transistors of a second channel type, different from the first channel type, to receive the plurality of bit signals. The transistors of the first channel type are configured to generate an XOR logic output based on the plurality of bit signals, and the transistors of the second channel type are configured to generate, substantially simultaneous with the generation of the XOR logic output, an XNOR logic output based on the plurality of bit signals. The compressor includes NAND gates to receive multiplicand and multiplier bit signals.
Claims16
A logic circuit, comprising:
- a first input terminal for receiving a first operand;
- a first switch having a gate terminal, wherein the gate terminal of the first switch is electrically coupled to the first input terminal;
- a first output terminal electrically coupled to a first terminal of the first switch;
- a second input terminal for receiving a second operand, wherein the second input terminal is electrically coupled to a second terminal of the first switch,
- a second switch having a first terminal, wherein the first terminal of the second switch is electrically coupled to a first terminal of a third switch, wherein the first terminal of the third switch is electrically coupled to a gate terminal of a fourth switch, wherein the first and second operands are transmitted at three different respective input terminals, and wherein a gate terminal of the second switch is electrically coupled to the second input terminal.
2 more elements
A logic circuit, comprising:
- a first input terminal for receiving a first operand;
- a first switch having a gate terminal, wherein the gate terminal of the first switch is electrically coupled to the first input terminal;
- a first output terminal electrically coupled to a first terminal of the first switch;
- a second input terminal for receiving a second operand, wherein the second input terminal is electrically coupled to a second terminal of the first switch;
- a second switch having a first terminal, wherein the first terminal of the second switch is electrically coupled to the second terminal of the first switch;
- a third switch having a terminal, wherein the terminal of the third switch is electrically coupled to a second terminal of the second switch;
- a third input terminal for receiving the first operand electrically coupled between the first terminal of the first switch and the first output terminal;
- and
- a second output terminal electrically coupled to the terminal of the third switch.
6 more elements
A circuit, comprising:
- input terminals for receiving first, second, third, and fourth operands;
- first and second output terminals for transmitting respective first and second output data signals;
- and
- logic circuitry coupled to the input and output terminals, wherein the first output data signal is a logic complement of the second output data signal, wherein respective transistors receiving the first and third operands are coupled between a ground voltage and a conductor transmitting the first output signal,
- wherein the logic circuitry comprises ten input terminals, and wherein each of the second and fourth operands are received at two of the input terminals, wherein respective transistors configured to receive the second and fourth operands are coupled in series between either a first output terminal and ground or a second output terminal and ground, and wherein:
- first, second, and third input terminals are solely configured to receive to the first operand;
- fourth, fifth, and sixth input terminals are configured to receive the third operand;
- seventh and eighth input terminals are configured to receive the second operand, and
- ninth and tenth input terminals are configured to receive the fourth operand.
6 more elements
A method comprising:
- receiving first, second, third and fourth input signals at input terminals of a circuit;
- and
- sending, from the circuit, first and second output signals corresponding to respective XOR and XNOR operations of the first, second, third, and forth input signals, wherein the circuit comprises first, second, third, and fourth switches, wherein a gate terminal of the first switch is electrically coupled to a first terminal, wherein a second terminal of a second switch is electrically coupled to a first terminal of third switch, wherein the first terminal of third switch is electrically coupled to a gate terminal of a fourth switch, and wherein the first and third input signals are transmitted at solely three different respective input terminals.
Dependencies are inferred from the claim text.