Charge locking circuits and control system for qubits

A method for controlling qubit gates configured to operate at a cryogenic temperature, wherein a controller for controlling the qubit gates comprises a plurality of charge locking circuits, wherein each of the plurality of charge locking circuits is configurable to provide a voltage signal to at least one qubit gate, and wherein each of the plurality of charge locking circuits comprises a first terminal for receiving an input voltage signal and a second terminal for selectively receiving a first voltage amount or a second voltage amount, and wherein the first voltage amount is greater than the second voltage amount, the method comprising:

• operating a first subset of the plurality of charge locking circuits in a capacitive mode such that the voltage signal output to at least one qubit gate comprises a pulse signal having a first controlled magnitude, wherein the first controlled magnitude depends on an amount of the input voltage signal and each of the first voltage amount and the second voltage amount;
• and
• operating a second subset of the plurality of charge locking circuits in a direct mode such that the voltage signal output to at least one qubit gate comprises a signal having a second controlled magnitude wherein the second controlled magnitude depends on the input voltage signal and only one of the first voltage amount or the second voltage amount.

A controller for qubit gates comprising:

• a control circuit configurable to operate at a cryogenic temperature, wherein the control circuit comprises a plurality of charge locking circuits, wherein each of the plurality of charge locking circuits is configurable to provide a voltage signal to at least one qubit gate, wherein each of the plurality of charge locking circuits comprises an input terminal for receiving an input voltage signal and an output terminal for selectively providing the voltage signal to the at least one qubit gate, and wherein the control circuit further comprises control logic configured to provide at least one control signal associated with each of the plurality of charge locking circuits, wherein each of the plurality of charge locking circuits further comprises a capacitor having a first terminal for receiving the input voltage signal and a second terminal for selectively receiving a first voltage amount or a second voltage amount, wherein the first voltage amount is greater than the second voltage amount.