Systems, devices and methods for power management and power estimation

A method of power management for a microcontroller, the method comprising:

• implementing, by a first core of the microcontroller, a system power transient management component,
• implementing, by one or more second cores of the microcontroller, one or more applications;
• wherein implementing by the first core of the system power transient management component comprises the system power transient management component:
• dynamically identifying an expected load transient event to occur in the microcontroller,
• determining power control data to optimize a response to the identified expected load transient event, the power control data comprising a power control mode and associated parameters, and
• providing the power control data to a power management integrated circuit (PMIC),
• wherein determining power control data to optimize the transient load response comprises:
• identifying a scenario from a plurality of predefined scenarios corresponding to the identified load transient event,
• determining, based on the determined scenario, one or more activities expected to occur based on the determined scenario,
• determining a dynamic current consumption profile comprising determining, based on the one or more determined activities, an estimated power consumption for each activity;
• obtaining runtime data for the one or more applications and update the dynamic current consumption profile based on runtime data;
• and
• determining the power control data based on the updated dynamic current consumption profile.

A hardware power estimator circuit for estimating power of an electronic device providing a plurality of (Intellectual Property) IP blocks, the hardware power estimator comprising:

• a hardware artificial neural network comprising a plurality of interconnected nodes arranged in one or more stages, wherein each individual stage comprising:
• a first input layer including values indicating activities of the electronic device and/or indicating active cells of the electronic device,
• a second input layer including a weighted set of values,
• an output layer including values calculated for the individual node stage;
• at least one intermediate layer situated between the input layer and the output layer, wherein each node of the at least one intermediate layer comprises a multiply and adder (MADD) circuit configured to calculate a value for the respective node using values received from the first and second input layers,
• wherein the hardware artificial neural network comprises one or more single individual stages, and the output layer of each single individual stage including values indicating a power estimation for one or more of plurality of IP blocks, or
• wherein the hardware artificial neural network comprises one or more multiple stages, each multiple node stage comprising a plurality of individual stages arranged in series so that the output layer of a non-final stage of the multiple stage serves as the first input layer for a following individual stage of the multiple stage, and the output layer a final individual stage includes values indicating a power estimation for one or more of the plurality of IP blocks of the electronic device,
• wherein each stage of the neural network is configured to operate in one clock cycle.