US 11,830,558 B2 · Memory device

Abstract

A memory device includes a first memory area including a first memory cell array having a plurality of first memory cells and a first peripheral circuit disposed below the first memory cell array; a second memory area including a second memory cell array having a plurality of second memory cells and a second peripheral circuit disposed below the second memory cell array; and a pad area including a power wiring. The first and second memory areas respectively include first and second local lockout circuits separately determining whether to lock out of each of the memory areas. The first and second memory areas are included in a single semiconductor chip to share the pad area, and the first and second memory areas operate individually. Accordingly, in the memory device, unnecessary data loss may be reduced by selectively stopping an operation of only a memory area requiring recovery.

Claims15

Dependent claims

A memory device, comprising:

a memory cell area in which a first MAT (Memory Array Tile) and a second MAT are disposed, each of the first MAT and the second MAT including a plurality of wordlines stacked on a first substrate in a vertical direction perpendicular to an upper surface of the first substrate and a plurality of channel structures penetrating the plurality of wordlines by extending in the vertical direction and connected to the first substrate;
a peripheral circuit area stacked with the memory cell area in the vertical direction, and including a second substrate and a plurality of semiconductor elements disposed on the second substrate;
a first local lockout circuit configured to determine whether to lock out the first MAT during an operation of the first MAT;
and
a second local lockout circuit configured to determine whether to lock out the second MAT, separately from the first MAT, during an operation of the second MAT.

2 more elements

An operating method of a memory device including a memory cell area in which a first MAT (Memory Array Tile) and a second MAT are disposed on a first substrate, a peripheral circuit area including peripheral circuits controlling the first MAT and the second MAT and stacked with the memory cell area in a vertical direction perpendicular to an upper surface of the first substrate, and a pad area receiving an external power voltage, comprising:

activating a second local lockout control signal, by a second local lockout circuit corresponding to the second MAT and maintaining a first local lockout control signal as a deactivated state, by a first local lockout circuit corresponding to the first MAT, when a second operating voltage is decreased based a decrease of the external power voltage;
stopping an operation of the second MAT, by the peripheral circuits of the peripheral circuit area, in response to the activation of the second local lockout control signal;
and
performing recovery for the second MAT, by the peripheral circuits of the peripheral circuit area.

1 more element

Dependencies are inferred from the claim text.

Memory device

Life of this patent

Memory device

Life of this patent

Abstract

Claims15