Directed interrupt virtualization with fallback
AssigneeInternational Business Machines Corporation
InventorsChristoph Raisch, Marco Kraemer, Donald William Schmidt, Bernd Nerz, Peter Dana Driever
Life of this patent
Estimating the term…
Abstract
A processor receives an interrupt signal. The interrupt signal is received with an interrupt target ID identifying a target processor for handling the interrupt signal. The processor is a target of the interrupt signal directly. A check is made as to whether the processor is the target processor identified by the interrupt target ID. The checking includes performing a comparison of the interrupt target ID with a current interrupt target ID assigned to the processor. Based on the checking being successful, the interrupt signal is accepted for handling by the processor.
Claims25
A computer program product for facilitating processing within a computing environment, the computer program product comprising:
- one or more computer readable storage media and program instructions collectively stored on the one or more computer readable storage media to perform a method comprising:
- receiving, by a processor of the computing environment, an interrupt signal, the interrupt signal being received with an interrupt target ID identifying a target processor for handling the interrupt signal, the processor being a target of the interrupt signal directly;
- checking whether the processor is the target processor identified by the interrupt target ID, the checking comprising performing a comparison of the interrupt target ID with a current interrupt target ID assigned to the processor;
- and
- broadcasting to one or more other processors of the computing environment the interrupt signal to be handled, based on the checking indicating that the interrupt target ID received with the interrupt signal does not match the current interrupt target ID assigned to the processor.
A computer system for facilitating processing within a computing environment, the computer system comprising:
- a memory;
- and
- at least one processor in communication with the memory, wherein the computer system is configured to perform a method, said method comprising:
- receiving, by a processor of the computing environment, an interrupt signal, the interrupt signal being received with an interrupt target ID identifying a target processor for handling the interrupt signal, the processor being a target of the interrupt signal directly;
- checking whether the processor is the target processor identified by the interrupt target ID, the checking comprising performing a comparison of the interrupt target ID with a current interrupt target ID assigned to the processor;
- and
- broadcasting to one or more other processors of the computing environment the interrupt signal to be handled, based on the checking indicating that the interrupt target ID received with the interrupt signal does not match the current interrupt target ID assigned to the processor.
A computer-implemented method of facilitating processing within a computing environment, the computer-implemented method comprising:
- receiving, by a processor of computing environment, an interrupt signal, the interrupt signal being received with an interrupt target ID identifying a target processor for handling the interrupt signal, the processor being a target of the interrupt signal directly;
- checking whether the processor is the target processor identified by the interrupt target ID, the checking comprising performing a comparison of the interrupt target ID with a current interrupt target ID assigned to the processor;
- and
- broadcasting to one or more other processors of the computing environment the interrupt signal to be handled, based on the checking indicating that the interrupt target ID received with the interrupt signal does not match the current interrupt target ID assigned to the processor.
Dependencies are inferred from the claim text.