Register scoreboard for a microprocessor with a time counter for statically dispatching instructions

A processor comprising:

• a clock circuit;
• a time counter storing a time count representing a current time of the processor, wherein the time count is incremented with each cycle of the clock circuit;
• an instruction issue unit coupled to the time counter for receiving a first instruction, and issuing a first instruction with a preset execution time based on the time count;
• and
• a register scoreboard storing a write time of a selected register from a plurality of registers in a register file, wherein the write time represents a future time relative to the time count;
• an instruction decode unit coupled to the register scoreboard, the instruction decode unit reading a write time for each source operand of the first instruction from the register scoreboard, and using the write times corresponding to the first instruction to determine an execution time for the first instruction;
• a time-resource matrix coupled to the register scoreboard and the time counter for storing information relating to available resources for each time count of the time counter, and
• an execution queue coupled to the time counter and the instruction issue unit to receive the first instruction from the instruction decode unit, and dispatch the first instruction to a functional unit when the preset execution time is correlated to the time count and source register associated with the first instruction is indicated by the register scoreboard as being valid or replay the first instruction if the write time of the source register in the register scoreboard is no longer correlated with the time count;
• wherein the available resources include at least one of:
• a plurality of read buses, a plurality of write buses, and a plurality of functional units.