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US 11,829,762 B2Granted
Time-resource matrix for a microprocessor with time counter for statically dispatching instructions
AssigneeSimplex Micro, Inc.
InventorThang Minh Tran
Life of this patent
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Abstract
A processor includes a time counter and a time-resource matrix and provides a method for statically dispatching instructions if the resources are available based on data stored in the time-resource matrix, and wherein execution times for the instructions use a time count from the time counter to specify when the instructions may be provided to an execution pipeline.
Claims24
A processor comprising:
- a time counter storing a time count representing a current time of the processor, wherein the time count is incremented periodically to count to a maximum time count;
- at least one time-resource register, having a number of entries wherein the number of entries equals the maximum time count, wherein each entry of the plurality of entries indicates an available resource count wherein a maximum value of the resource count is a total number of a type of a resource;
- an instruction issue unit coupled to the time counter for receiving a first instruction, and issuing the first instruction with a preset execution time based on the time count, providing that the resource count of a time-resource register indicates available resources at the preset execution time, but stalling the first instruction if any resource required by the first instruction is not available at the preset execution time;
- and
- an execution queue coupled to the time counter and the instruction issue unit to receive the first instruction from the instruction issue unit, and dispatch the first instruction to a functional unit when the preset execution time corresponds to the time count.
2 more elements
A processor comprising:
- a clock circuit;
- a time counter storing a time count representing a specific time of operation of the processor, wherein the time count is incremented by the clock circuit;
- a time-resource matrix coupled to the register scoreboard and the time counter for storing information relating to available resources for each time count of the time counter, and
- an instruction issue unit coupled to the time counter for receiving a first instruction, and issuing or stalling the first instruction based on availability of the available resources from the time-resource matrix at a preset execution time based on the time count;
- and
- an execution queue coupled to the time counter and the instruction issue unit to receive the first instruction from the instruction issue unit, and dispatch the first instruction to a functional unit when the preset execution time matches the time count;
- a register scoreboard storing a write time of a selected register from a plurality of registers in a register file, wherein the write time is a future time specified by the time count;
- an instruction decode unit coupled to the register scoreboard, the instruction decode unit reading a write time for each source operand of the first instruction from the register scoreboard, and using the write times corresponding to the first instruction to determine an execution time for the first instruction;
- and
- wherein the available resources include at least one of a plurality of read buses, a plurality of write buses, and a plurality of functional units.
7 more elements
A method implemented in a processor, the method comprising:
- issuing an instruction to an execution queue or stalling execution of the instruction in an instruction issue unit;
- and
- executing the instruction at a future time depending on the availability of resources specified in a time-resource matrix, wherein the future time is a time defined by a time count from a time counter, which is incremented with each clock cycle of a clock circuit.
Dependencies are inferred from the claim text.