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US 11,829,187 B2Granted
Microprocessor with time counter for statically dispatching instructions
AssigneeSimplex Micro, Inc.
InventorThang Minh Tran
Life of this patent
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Abstract
A processor includes a time counter and provides a method for statically dispatching instructions with preset execution times based on a time count from the time counter provided to an execution pipeline.
Claims33
A processor comprising:
- a time counter storing a time count representing a current time of the processor, wherein the time count is incremented with each clock cycle of a clock circuit;
- an instruction issue unit coupled to the time counter for receiving a first instruction, and issuing the first instruction with a preset execution time based on the time count;
- and
- an execution queue coupled to the time counter and the instruction issue unit to receive the first instruction from the instruction issue unit, and dispatch the first instruction to a functional unit when the preset execution time is correlated to the time count.
1 more element
A processor comprising:
- a clock circuit;
- a time counter storing a time count representing a current time of the processor, wherein the time count is incremented with each cycle of the clock circuit;
- an instruction issue unit coupled to the time counter for receiving a first instruction, and issuing the first instruction with a preset execution time based on the time count;
- an execution queue coupled to the time counter and the instruction issue unit to receive the first instruction from the instruction issue unit, and dispatch the first instruction to a functional unit when the preset execution time is correlated to the time count;
- a register scoreboard storing a write time of a selected register from a plurality of registers in a register file, wherein the write time is a future time based on the time count;
- an instruction decode unit coupled to the register scoreboard, the instruction decode unit reading a write time for each source operand of the first instruction from the register scoreboard, and using the write times corresponding to the first instruction to determine an execution time for the first instruction;
- a time-resource matrix coupled to the register scoreboard and the time counter for storing information relating to available resources for each time count of the time counter and
- wherein the available resources include at least one of:
- a plurality of read buses, a plurality of write buses, and a plurality of functional units.
6 more elements
A method executed by a processor comprising:
- issuing an instruction to an execution queue in the processor;
- and
- executing the instruction at a future time wherein the future time is a time based on a time count from a time counter which is incremented with each clock cycle of a clock circuit.
A processor comprising:
- a time counter storing a time count representing a current time of the processor, wherein the time count is incremented with each clock cycle of a clock circuit;
- an instruction issue unit coupled to the time counter for receiving a first instruction, wherein the first instruction requires a plurality of resources to be available for execution, the instruction issue unit issuing the first instruction with a preset execution time at a time count at which the plurality of resources for execution of the first instruction are available;
- and
- an execution queue coupled to the time counter and the instruction issue unit to receive the first instruction from the instruction issue unit, and dispatch the first instruction to a functional unit when the preset execution time is correlated to a value of the time count.
1 more element
Dependencies are inferred from the claim text.