Wireless circuitry with self-calibrated harmonic rejection mixers

A non-transitory computer-readable storage medium storing one or more programs configured to be executed by at least one processor, the one or more programs including instructions that, when executed by the at least one processor, cause the at least one processor to:

• use a first mixer to mix a first signal with a second signal that is phase-delayed with respect to the first signal;
• use a second mixer to mix the second signal with a third signal that is phase-delayed with respect to the second signal;
• and
• use at least the first and second mixers to output a direct current (DC) voltage onto an output path based on the first signal and the second signal.

Wireless circuitry comprising:

• a first path;
• a second path;
• a delay line configured to generate a set of signals;
• mixers coupled between the first path and the second path, the mixers being configured to generate a radio-frequency signal on the second path based on an input on the first path and based on the set of signals generated by the delay line;
• and
• an adjustable load coupled to the second path.

A method of operating wireless circuitry, the method comprising:

• with a first mixer, mixing a first signal with a second signal that is phase-delayed with respect to the first signal;
• with a second mixer, mixing the second signal with a third signal that is phase-delayed with respect to the second signal;
• and
• with at least the first and second mixers, outputting a direct current (DC) voltage onto an output path.