Error correction using soft decision bits and multiple hypotheses
AssigneeSamsung Electronics Co., Ltd.
InventorsMichael John Cowell, David Skinner Price
Life of this patent
Estimating the term…
Abstract
An apparatus and method for error correction based on soft decision bits and multiple hypotheses includes: maintaining a plurality of previous single bit-flip hypotheses, each hypothesis including a respective bit-flip, a respective pre-flip bit confidence, and a respective hash responsive to the respective bit-flip; receiving a bit and a corresponding bit confidence; comparing the received bit confidence with a highest pre-flip bit confidence of the maintained plurality of single bit-flip hypotheses; and if the received bit confidence is less than the highest pre-flip bit confidence, forming a new single bit-flip hypothesis and replacing a prior bit-flip hypothesis having the highest pre-flip bit confidence with the new hypothesis.
Claims11
An error correction apparatus configured to receive a plurality of packets, each packet comprising a plurality of symbols, and each symbol comprising a plurality of bits, and correct at least one flipped bit based on soft decision bits and multiple hypotheses, the apparatus comprising:
- a hard decoding block configured to receive a plurality of bits of a current symbol and compute a first hash of the plurality of bits of the current symbol, wherein the hard decoding block includes an input buffer and a first hash circuit connected to the input buffer;
- and
- a soft decoding block configured to receive the plurality of bits of the current symbol, invert an incoming bit, and compute at least one second hash of the bits including the inverted incoming bit, wherein the soft decoding block includes an inverter connected to the input buffer, a second hash circuit connected to the first hash circuit and the inverter, a tracking array connected to the input buffer, a frame tracking circuit connected to the tracking array, a soft decision circuit connected to the frame tracking circuit, a weak bit search circuit connected to the frame tracking circuit and the tracking array, and a symbol counter connected to the tracking array.
An error correction system configured to receive a plurality of packets, each packet comprising a plurality of symbols, and each symbol comprising a plurality of bits, and to correct at least one flipped bit based on soft decision bits and multiple hypotheses, the system comprising:
- a hard decoding block configured to receive a plurality of bits of a current symbol and compute a first hash of the plurality of bits of the current symbol, wherein the hard decision block includes an input buffer and a first hash circuit connected to the input buffer;
- and
- a soft decoding block configured to receive the plurality of bits of the current symbol, invert an incoming bit, and compute at least one second hash of the bits including the inverted incoming bit, wherein the soft decoding block includes an inverter connected to the input buffer, a second hash circuit connected to the first hash circuit and the inverter, a tracking array connected to the input buffer, a frame tracking circuit connected to the tracking array, a soft decision circuit connected to the frame tracking circuit, a weak bit search circuit connected to the frame tracking circuit and the tracking array, and a symbol counter connected to the tracking array,
- wherein the tracking array is configured to store hashes of a plurality of single-bit hypotheses, read a stored hash from each element of the tracking array, progress each read hash on each incoming bit, overwrite each stored hash in the array with each progressed hash, respectively, check, at the end of a packet, if any of the single-bit hypotheses hash elements in the tracking array is zero, and if not, make a plurality of corrections by computing at least one affine combination of the array hashes to correct a plurality of flipped bits based on the plurality of hashes,
- wherein the tracking array is further configured to check, at the end of a packet, if any of hashes of the plurality of single-bit hypotheses in the tracking array is zero, and if not, make a plurality of corrections by computing at least one affine combination of hashes of the tracking array to correct a plurality of flipped bits based on the hashes of the plurality of single-bit hypotheses,
- wherein the at least one affine combination of the hashes of the tracking array is a linear combination of hashes of the tracking array.
Dependencies are inferred from the claim text.