US 11,824,535 B2 · Fail-safe counter evaluator to insure proper counting by a counter

Abstract

A fail-safe counter evaluator is provided to insure proper counting operations by fail-safe counters. The failsafe counter evaluator comprises a first microprocessor, a first counter, a second counter, a second microprocessor and a test channel. The first counter is configured as a counter in operation and disposed in the first microprocessor to receive externally generated count pulses. The second counter is disposed in the first microprocessor and configured to undergo a test. The test channel is configured to send an input test signal to the second counter based on test pulses from the second microprocessor. The first microprocessor and the second microprocessor are synchronized so that to coordinate a start and an end of the test. The second counter is evaluated after the test pulses have been sent to determine if the second counter is operating properly.

Claims20

Dependent claims

A failsafe counter evaluator to insure proper counting, the failsafe counter evaluator comprising:

a first microprocessor;
a first counter configured as a counter in operation and disposed in the first microprocessor to receive externally generated count pulses;
a second counter is disposed in the first microprocessor and configured to undergo a test;
a second microprocessor;
and
a test channel is configured to send an input test signal to the second counter based on test pulses from the second microprocessor,
wherein the second microprocessor is configured to inject the input test signal to the second counter of the first microprocessor being the counter under test such that the first microprocessor and the second microprocessor are synchronized so that to coordinate a start and an end of the test, and
wherein the first counter is driven by the externally generated count pulses to be counted while the second counter is sent the test pulses for evaluation such that the second counter is evaluated after the test pulses have been sent to determine if the second counter is operating properly.

5 more elements

A fail-safe counter evaluator to ensure proper counting, the fail-safe counter evaluator comprising:

a first microprocessor configured to provide internally generated test pulses for evaluating counters to insure proper counting operations;
a test channel configured to send an input test signal based on the test pulses from the first microprocessor;
a second microprocessor;
a second counter configured as a counter under test and disposed in the second microprocessor;
and
a first counter disposed in the second microprocessor and configured to count externally generated count pulses,
wherein the first microprocessor is configured to inject the input test signal to the second counter being the counter under test such that the first microprocessor and the second microprocessor are synchronized so that to coordinate a start and an end of the test, and
wherein the first counter is driven by the externally generated count pulses to be counted while the second counter is sent the test pulses for evaluation such that the second counter is evaluated after the test pulses have been sent to determine if the second counter is operating properly.

5 more elements

Dependencies are inferred from the claim text.

Fail-safe counter evaluator to insure proper counting by a counter

Life of this patent

Fail-safe counter evaluator to insure proper counting by a counter

Life of this patent

Abstract

Claims20