Reprogrammable quantum processor architecture

A quantum computing machine, comprising:

• at least one classic computing core incorporating control circuitry and at least one quantum computing core both operated at a cryogenic temperature, wherein said at least one classic computing core and said at least one quantum computing core are fabricated on a monolithic semiconductor integrated circuit die;
• an interface system on chip (SoC) in communication with at least one of said at least one classic computing core and said at least one quantum computing core, wherein said interface SoC is operated at an intermediate temperature higher than said cryogenic temperature;
• at least one of a programmable pattern generator and a memory based sequence execution unit operative to control said at least one quantum computing core;
• and
• wherein said intermediate temperature comprises a temperature between 30 and 78 kelvin.

A quantum computing machine, comprising:

• at least one classic computing core and at least one quantum computing core operated at a cryogenic temperature and including a plurality of charge qubits, said at least one classic computing core and said at least one quantum computing core fabricated on a monolithic semiconductor integrated circuit die;
• an external support unit in communication with said at least one classic computing core and said at least one quantum computing core;
• a pulse generator operative to generate control pulses in accordance with one or more sequences from a re-programmable pattern generator for controlling a plurality of quantum dots in said at least one quantum computing core;
• and
• a partial readout unit operative to generate a partial readout of a quantum state that is re-injected back into at least one of said at least one classic computing core and said at least one quantum computing core thereby extending quantum decoherence time.