US 11,817,878 B2Granted

Multi-channel decoder with distributed scheduling

AssigneeMaxLinear, Inc.

InventorsGert Schedelbeck, Stefan Uhlemann

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Abstract

A multi-channel decoder circuit associated with a multi-channel decoder system is disclosed. The multi-channel decoder circuit comprises a distributed decoder circuit comprising a set of unit decoder circuits, each unit decoder circuit configured to receive one or more codewords of a plurality of codewords associated with a plurality of input channels, and decode the one or more codewords. The multi-channel decoder circuit further comprises a distribution controller circuit configured to distribute each incoming codeword of the one or more codewords to the respective unit decoder circuit of the set of unit decoder circuits within the distributed decoder circuit, based on determining a currently available unit decoder circuit within the set of unit decoder circuits.

Claims29

Dependent claims

A multi-channel decoder circuit, comprising:

a distributed decoder circuit comprising a set of unit decoder circuits, each unit decoder circuit configured to receive one or more codewords of a plurality of codewords associated with a plurality of input channels, and iteratively decode the one or more codewords, a number of iterations being based on a latency target;
and
a distribution controller circuit configured to distribute an incoming codeword of the one or more codewords to the respective unit decoder circuit of the set of unit decoder circuits within the distributed decoder circuit, based on a predefined condition, the predefined condition relating to a quality-of-service (QoS) class of the incoming codeword, the plurality of codewords being distributed based on determining a currently available unit decoder circuit within the set of unit decoder circuits and based on the respective QoS class, a particular codeword being distributed specifically to the currently available unit decoder circuit based on a particular QoS class for the particular codeword.

A multi-channel decoder system, comprising:

a multi-channel decoder circuit comprising:
a distributed decoder circuit comprising a set of unit decoder circuits distributed between at least two separate hardware devices, each unit decoder circuit configured to receive one or more codewords of a plurality of codewords associated with a plurality of input channels, and decode the one or more codewords;
and
a distribution controller circuit configured to distribute an incoming codeword of the one or more codewords to the respective unit decoder circuit of the set of unit decoder circuits, based on determining a currently available unit decoder circuit within the set of unit decoder circuits and based on a capability of the currently available unit decoder circuit to decode a particular codeword, the capability relating to a predefined condition, and based on a respective predefined quality-of-service (QoS) class for the incoming codeword, the particular codeword being distributed specifically to the currently available unit decoder circuit based on a particular QoS class for the particular codeword.

1 more element

A method for a multi-channel decoder circuit, comprising:

receiving, at each unit decoder circuit of a set of unit decoder circuits, one or more codewords of a plurality of codewords associated with a plurality of input channels, and iteratively processing the one or more codewords;
and
distributing an incoming codeword of the one or more codewords to the respective unit decoder circuit of the set of unit decoder circuits, by a distribution controller circuit, based on a predefined condition, the predefined condition relating to a quality-of-service (QoS) class of the incoming codeword, the plurality of codewords being distributed based on determining a currently available unit decoder circuit within the set of unit decoder circuits, and based on a respective predefined QoS class for the incoming codeword, wherein distributing the incoming codeword of the one or more codewords to the respective unit decoder circuit of the set of unit decoder circuits includes distributing a particular codeword specifically to the currently available unit decoder circuit based on a particular QoS class for the particular codeword.

Dependencies are inferred from the claim text.

Facts

Application: 16/196,422Filed 20 Nov 2018
Published: US 2019/0089373 A121 Mar 2019
Granted: 14 Nov 2023
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

H03M 13/114
Scheduling of bit node or check node processing: shuffled, staggered, layered or turbo decoding schedules
H03M 13/1102
Using multiple parity bits: codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
H03M 13/3707
Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35: adaptive decoding and…
H03M 13/3715
Adaptive decoding and hybrid decoding, e.g. decoding methods or techniques providing more than one decoding algorithm for one code: adaptation to…